About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

• Manage Physical design of SoC to Tape out while working with multiple team members.

• Evaluate and develop physical design methodologies and decide on the SoC flow.

• Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade-offs for physical design closure.

• Participate in design reviews and track issue resolution, and engage in technical and schedule trade-off discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.

• Understand architecture and design specifications with the team, and define physical design strategies to meet quality and schedule goals.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience in ASIC design implementation flows and chip integration.

• 8 years of Management experience in ASIC development teams.

• Experience executing low-power physical design implementation using industry-standard synthesis and Static Timing Analysis (STA) tools.

• Experience in sign-off convergence including STA, electrical checks, and physical verification.

Preferred qualifications

• Experience in leading physical design teams working on digital designs.

• Experience in engineering across physical design, implementation, GDS tape-out.

• Experience in floorplanning, block integration, static timing analysis, sign-off.

• Knowledge of delivery of silicon in technology process nodes and Ability to lead cross-functional teams.

• Understanding of Circuit design, device physics and deep sub-micron technology.