• Design and simulate superconductor digital logic circuits (such as single flux quantum (SFQ) logic, adiabatic quantum flux parametron (AQFP) logic, and other emerging superconductor logic families) for generating waveforms tailored to qubit control and readout.

• Develop superconductor digital logic systems enabling multiplexed qubit control and readout.

• Address issues in the integration of superconductor digital electronics such as multi-layer cell design, full-chip clock synchronization, flux trapping, and signal integrity.

• Collaborate with teams focused on design, fabrication, and measurement to validate fully integrated quantum processors.

• Publish research papers and present at leading scientific conferences to advance and enhance publicity.

Applicants in San Francisco: Qualified applications with arrest or conviction records will be considered for employment in accordance with the San Francisco Fair Chance Ordinance for Employers and the California Fair Chance Act.
In accordance with Washington state law, we are highlighting our comprehensive benefits package, which is available to all eligible US based employees. Benefits for this role include:

• Health, dental, vision, life, disability insurance

• Retirement Benefits: 401(k) with company match

• Paid Time Off: 20 days of vacation per year, accruing at a rate of 6.15 hours per pay period for the first five years of employment

• Sick Time: 40 hours/year (increased to 69 hours/year for Seattle) including 5 discretionary sick days per instance

• Maternity Leave (Short-Term Disability + Baby Bonding): 28-30 weeks

• Baby Bonding Leave: 18 weeks

• Holidays: 13 paid days per year

• Master's degree in Electrical Engineering, Physics, related engineering discipline, or equivalent practical experience.

• Experience in superconductor logic families (e.g., RSFQ, ERSFQ, RQL, HFQ, AQFP).

• Experience performing tape-out of a superconducting IC chip.

• One or more published research paper or presentation at a relevant scientific conference.