
Organizing the world's information and making it universally accessible.
Senior ASIC RTL Engineer, Subsystem Integration
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Collaborate with Architecture teams and define the microarchitecture of complex Subsystems including interface protocols, block diagrams, and data flow.
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Develop RTL implementations (verilog/system verilog) and create the required subsystem that meets competitive Power, Performance, and Area (PPA) targets.
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Perform RTL quality checks such as Lint, CDC, RDC, SDC and UPF checks.
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Participate in debugs with the verification team to ensure a functional design. Own power analysis and optimization for the subsystem, ensuring exceptional PPA.
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Lead a team of engineers to ensure high quality, on time delivery of subsystems.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
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8 years of experience in RTL design using Verilog/System Verilog.
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8 years of experience in subsystem microarchitecture creation, RTL integration and delivery.
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Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC, VCLP, synthesis).
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关于Google

Google specializes in internet-related services and products, including search, advertising, and software.
10,001+
员工数
Mountain View
总部位置
$1,700B
企业估值
评价
10条评价
4.5
10条评价
工作生活平衡
3.2
薪酬
4.3
企业文化
4.1
职业发展
4.2
管理层
3.8
82%
推荐率
优点
Great benefits and perks
Innovative and interesting work
Career development and learning opportunities
缺点
High pressure and expectations
Long hours and heavy workload
Fast-paced and overwhelming environment
薪资范围
57,503个数据点
Mid/L4
Mid/L4 · Accessibility Analyst
1份报告
$214,500
年薪总额
基本工资
$165,000
股票
-
奖金
-
$214,500
$214,500
面试评价
9条评价
难度
3.4
/ 5
时长
14-28周
录用率
44%
体验
正面 0%
中性 56%
负面 44%
面试流程
1
Application Review
2
Online Assessment/Technical Screen
3
Phone Screen
4
Onsite/Virtual Interviews
5
Team Matching
6
Offer
常见问题
Coding/Algorithm
System Design
Behavioral/STAR
Technical Knowledge
Product Sense
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