About the job

We are seeking a Lithography and Etch Process Lead to join our talented team in Silicon Valley. Raxium's technology is based on GaN-on-Si micro-LEDs, with more demanding process requirements than those found in typical LED fabs, and an installed equipment set to meet those needs.In this role, you will select, motivate, set priorities, develop, and manage individual performance to ensure functional excellence and highly engaged team members. You will contribute to the innovation behind products loved by billions worldwide and be a part of a team as we develop a truly novel display technology.

Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets.

The US base salary range for this full-time position is $237,000-$329,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Own the Lithography and Etch process engineering areas, ensuring seamless transitions from proof-of-concept to manufacturing, which is now underway.

• Drive the wafer fab roadmap and deliver key performance indicators (KPIs) by overseeing process innovation, new tool installations, and process capability enhancements.

• Utilize Statistical Process Control (SPC), Failure Mode and Effects Analysis (FMEA), and structured problem-solving (RCA) to eliminate systemic bottlenecks and enhance lithography and etch module stability.

• Implement equipment and process optimization to maximize production efficiencies and optimize wafer output.

• Serve as the primary technical liaison for fab operations, ensuring safety, quality, and manufacturability standards are consistently exceeded. Drive an engaged engineering culture through proactive performance management and talent development.

Minimum qualifications

• Master's degree in Electrical Engineering, Optics, Physics, Materials Science, a related technical field, or equivalent practical experience.

• 15 years of experience in semiconductor lithography and compound semiconductor etch process engineering in high-volume semiconductor wafer fab manufacturing.

• 10 years of technical leadership experience with or without direct reports in semiconductor wafer fabrication.

• Experience in semiconductor optoelectronics devices and device fabrication.

Preferred qualifications

• PhD degree in Electrical Engineering, Optics, Physics, Materials Science, a related technical field, or equivalent practical experience.

• Experience in the process integration of optoelectronics devices.

• Experience defining the process strategy and execution, taking initiative in engineering cross-functions, influencing executive stakeholders, and managing communication.

• Experience as a Six Sigma Black Belt practitioner utilizing structured problem-solving, data querying, and analysis.