• Manage Register-Transfer Level (RTL) design, Design Verification (DV) and physical design of System-on-Chip (SoC) to tape-out while working with multiple team members.

• Evaluate and develop SoC design and Integration methodologies and decide on the SoC flow.

• Work with architects and reasoning designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade-offs for physical design closure.

• Participate in design reviews and track issue resolution, and engage in technical and schedule trade-off discussions. Create execution plans for projects and manage team efforts from concept to working silicon in volume.

• Understand architecture and design specifications with the larger team, and define physical design strategies and tactics to meet quality and schedule goals.

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be responsible for overseeing the design and development of chips for the products. You will be responsible for leading the chip design end-to-end, from architecture requirements up to tape-out.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.

• 10 years of experience with silicon design, DV, implementation and chip integration.

• Experience with management in Application-Specific Integrated Circuit (ASIC) development teams.

• Experience in leading design teams with working on digital designs that have taped-out and produced working silicon and delivering silicon.