About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly complex digital or mixed-signal chips or IPs. You will define DFT architecture, and create DFT flows for complex next generation So Cs in partnership with the Design and Physical Design teams. You will also be responsible for design verification of test logic, test pattern generation and debugging and test coverage issues.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Complete all Test Design Rule Checks and Design changes to fix TDRC violations to achieve high test quality.

• Insert DFT logic, including scan chains, MBIST, TAP controller, Clock Control block, and other DFT IP blocks.

• Insert and hook up MBIST logic including test collar around memories, MBIST controllers, e Fuse logic and connect to core and TAP interfaces.

• Design Verification of DFT logic and test pattern generation.

• Design and Implement System Level Test strategy.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

• 3 years of experience in DFT architecture, implementation, ATPG, and verification for So Cs.

• Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.

• Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, Test Kompress).

• Experience with silicon process and technology nodes for high speed and low power consumption.

• Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).