Complete all Test Design Rule Checks and Design changes to fix TDRC violations to achieve high test quality.

Insert DFT logic, including scan chains, MBIST, TAP controller, Clock Control block, and other DFT IP blocks.

Insert and hook up MBIST logic including test collar around memories, MBIST controllers, e Fuse logic and connect to core and TAP interfaces.

Design Verification of DFT logic and test pattern generation.

Design and Implement System Level Test strategy.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

3 years of experience in DFT architecture, implementation, ATPG, and verification for So Cs.

Experience with industry-standard test methodologies and platforms, such as (but not limited to) ATE, MBIST, JTAG, or System Level Test (SLT).