About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define and document the comprehensive DFT architecture for multi-core So Cs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, functional BISTs, Analog components, logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.

• Lead the complete DFT lifecycle from RTL planning to pattern handoff, own the schedule, resource allocation, and milestone tracking to ensure zero-defect delivery.

• Deploy next-generation DFT methodologies and automation flows to maximize test coverage, while minimizing test time, pattern count, and silicon area overhead. Collaborate with post silicon team, Physical Design and Power Architects.

• Support the post-silicon phase to achieve final Production Release Qualification (PRQ).

• Mentor the technical staff, drive vendor EDA tool selection/qualification, and act as the primary technical liaison for DFT matters with stakeholders.

Minimum qualifications

• Bachelor’s degree in Electrical or Computer Engineering, or equivalent practical experience.

• 8 years of experience in SoC DFT architecture.

• 8 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).

• Experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.

• Experience leading multiple SoC projects from RTL architecture through to post-silicon validation and PRQ.

• Experience scripting in Tcl, Python, or Perl for developing automation flows.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering with a focus on VLSI Testing, Fault Tolerance, Reliability, or a related field.

• Experience with advanced technology nodes (5nm/3nm), 2.5D/3D-IC packaging, or high-speed I/O (Ser Des/DDR) testing methodologies.

• Experience managing global technical teams and driving vendor engagement.

• Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs.