About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be focused on the functional design verification of multi-core System-on-a-chip (SoC) architectures. You will be responsible for maintaining data consistency across memory hierarchies, with a particular emphasis on the integration of ARM cores, coherent interconnects, and Input/Output (I/O) subsystems. You will be responsible for defining verification strategy, developing random environments, and driving coverage closure for system level coherent scenarios.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Verify designs using verification techniques and methodologies.

• Work cross-functionally to debug failures and verify the functional correctness of the design.

• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 4 year of experience with System Verilog/Universal Verification Methodology (UVM) and coherency concepts.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.

• Experience using formal techniques (e.g., Jasper Gold or Verification Compiler (VC) Formal) for verifying cache state transitions, credit management, and deadlock scenarios.

• Experience in defining and closing functional coverage for multi-agent coherency scenarios.

• Experience with correlating pre-silicon coherency bugs with post-silicon silicon sightings using trace buffers or reasoning analyzers.