About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Circuit Design Engineer and Foundry Interface you will collaborate with our foundry partners as well as our technology, circuits, physical design, and front end teams to overcome and deliver cutting-edge ASIC’s and SoC’s. You will drive engaged and reliable products by identifying the optimal process nodes, methodologies, and IPs for our designs.

You will further support on time and high quality delivery of design kits, IPs, and related collaterals to our internal teams and design flows. You will develop novel high performance computing design methodologies that co-optimize across the entire design space, then see these through from inception to maturity and tapeout.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $183,000-$271,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Lead technical evaluations of advanced process nodes and drive the strategy for custom circuits and memories/SRAMs to hit power-performance-area (PPA) goals.

• Engage with foundry partners to receive and debug necessary collaterals for design kits, standard cells, memories, other IPs, and more.

• Provide technical mentorship and guidance to circuit and physical design teams, overseeing the design and verification of custom circuits.

• Define optimal methodologies by investigating performance, power, and area across different technology nodes and implementation techniques.

• Collaborate with our circuits, physical design, logic design, and technology teams in advanced CMOS nodes to ensure standard cell libraries and memories/SRAMs are seamlessly integrated.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience in process technology, circuit design, and physical design disciplines.

• Experience with advanced process technology nodes, including yield and reliability, design kit and IP collaterals, and evaluating power, performance, and area.

• Experience with custom circuit/IP and physical design spaces.

• Experience in transistor level design in advanced finfet nodes for standard cells and memories/SRAMs, including SPICE simulations and characterization methodology.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.

• 15 years of experience and a track record of delivering circuit and physical design solutions, including across standard cells and memories/SRAMs, leading to product tapeout.

• Experience with programming/scripting (Python, TCL).

• Understanding of semiconductor device physics and transistor characteristics.

• Proven track record of technical leadership, guiding teams through design and tapeout and interfacing with foundry suppliers.

• Strong documentation, presentation, and communication skills.