About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive Tensor Processing Unit (TPU) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML- driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Participate in the design, implementation and integration of Chassis, subsystems and SoC.

• Perform RTL coding, function/performance simulation debug, and Lint/Clock-Domain Crossing (CDC)/Formal Verification(FV)/Unified Power Format (UPF) checks.

• Participate in design debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams.

• Coordinate with various IP teams to meet schedule and quality requirements.

• Communicate and work with multi-disciplined and multi-site teams.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.

• 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or System Verilog.

• Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.

• Experience in SoC designs and integration flows.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.

• Experience with a scripting language like Perl or Python.

• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.