Title: GPIO Circuit Design Engineer About Global Foundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction:

This position is for IO Design and Characterization Engineer who will own End-to-End development of IO IPs. The successful candidate needs to have an exceptional background in CMOS design, End-to-end Analog/IO IP development experience, and needs to be a team player with a solution-oriented approach.

Essential Responsibilities:

• Responsible for the development and delivery of IO IPs (GPIO, LVDS, SSTL, HSTL, MIPI, etc) in multiple technology nodes and achieving corresponding PPA indicators
• Responsible for collaborating to defining IO IP architecture design and circuit design, simulation verification and reliability assurance
• Collaborate in the design and implementation of test chips, packaging design, test board design, post-silicon testing, and qualification
• Participate in market competition analysis and product definition
• Supervise layout engineers and ensure the delivery of high-quality layouts
• Drive a culture of innovation

Other Responsibilities:

• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements, and programs

Required Skills & Qualifications:

• Bachelor's or master's degree in Electronics engineering, or related field.
• 3+ years of experience in semiconductor IP design
• Deep understanding of digital and mixed-signal IO design principles.
• Knowledge of process technology impact on circuit design is a plus
• High Speed I/O Design is also plus.
• Experience with RTL design (Verilog/VHDL), synthesis, and timing closure.
• Familiarity with ESD, pad ring design, and physical verification flows.
• Strong project management and communication skills.
• Experience with silicon validation and lab debug tools is a plus.

Preferred Qualifications:

• Prior experience managing GPIO or similar IO IP blocks.
• Knowledge of low-power design techniques and IO reliability.

Global Foundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard.

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities.

All offers of employment with Global Foundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia