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Senior/Staff Hardware Digital Engineer (HDL)
Bayan Lepas, Pulau Pinang, Malaysia, MY
·
On-site
·
Full-time
·
5mo ago
Summary
You will be a member of NI Product R&D Team, essential to design the next generation of cutting-edge NI PXI modularized high speed, mixed signal and high precision I/O test instrument, supporting wide arrays of test application that is critical to complete NI test system offering in EV, ADAS, Aerospace, Semiconductor and Electronics. You will be involved throughout the product development from pathfinding research phase till post product release. You will work closely with the product architects, project managers, technical leads, engineers with various expertise to craft and implement the designs. This position involves a wide range of engineering activities such as high-speed subsystem design, design simulation, design validation and verification, debugging circuit and system level problems.
In this Role, Your Responsibilities Will Be:
- Developing hardware features based on requirement from product management
- FPGA and CPLD development
- Technology research, Products bring-up, validation, verification and debugging to enable successful product launch
- Debugging and resolving system level issues
- Work with Board level designer on circuit design, schematics capture, layout review, simulation and signal integrity analysis
Who You Are:
You demonstrate strong initiative in challenging situations and excel at recognizing and acting on opportunities. You streamline tasks and create efficient workflows. Your communication is adaptable, aligning content and style to suit various parties, and you adjust quickly to changing circumstances.
For This Role, You Will Need:
- Bachelor's or Master's degree in Electrical/Electronic Engineering is required
- Minimum 5 years of VHDL/Verilog/System Verilog design experience for Senior Level
- Minimum 2 years of VHDL/Verilog/System Verilog design experience for Staff Level
Preferred Qualifications that Set You Apart:
- Passionate in continuous learning and working with analog, digital, & other computer technologies
- HDL IP design with FPGAProficient in VHDL/Verilog/System Verilog development
- Experience in testbench development is a plus
- Test automation expertise with scripting/programming language
- Board level design experience is a plus
Our Culture & Commitment to You:
At Emerson, we prioritize a workplace where every employee is valued, respected, and empowered to grow. We foster an environment that encourages innovation, collaboration, and diverse perspectives—because we know that great ideas come from great teams. Our commitment to ongoing career development and growing an inclusive culture ensures you have the support to thrive. Whether through mentorship, training, or leadership opportunities, we invest in your success so you can make a lasting impact. We believe diverse teams, working together are key to driving growth and delivering business results.
We recognize the importance of employee wellbeing. We prioritize providing competitive benefits plans, a variety of medical insurance plans, Employee Assistance Program, employee resource groups, recognition, and much more. Our culture offers flexible time off plans, including paid parental leave (maternal and paternal), vacation and holiday leave.
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About Emerson

Emerson
PublicEmerson Electric is a diversified global technology and industrial company providing innovative solutions for customers in industrial, commercial and residential markets.
10,001+
Employees
St. Louis
Headquarters
Reviews
3.5
10 reviews
Work Life Balance
3.2
Compensation
2.8
Culture
3.5
Career
3.8
Management
3.0
65%
Recommend to a Friend
Pros
Good benefits and compensation packages
Supportive and helpful colleagues
Growth and learning opportunities
Cons
Management and leadership issues
Below market pay and compensation
Fast-paced work environment pressure
Salary Ranges
600 data points
Junior/L3
Senior/L5
Junior/L3 · Data Visualization Analyst
1 reports
$143,000
total / year
Base
$110,000
Stock
-
Bonus
-
$143,000
$143,000
Interview Experience
2 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
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