ASIC/SoC Physical Design Engineer - Python/Perl/TCL/Shell Scripts - 7 to 12 years - Bangalore at Cisco

Meet the Team

Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry.

You will work with Cisco's best-in-class Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.

We are looking for a talented and experienced Design Verification Lead to join our team and drive verification of Cisco's silicon photonics driver integrated circuits for the next generation of products for 100/200/400G per Lambda solutions.

Your Impact

• Assist in RTL/netlist‑to‑GDSII implementation for block‑level and full‑chip designs in advanced technology nodes.
• Support digital implementation flows and collaborate with EDA tool vendors to debug issues.
• Support in developing hierarchical floorplans, macro placement, I/O planning, congestion, timing, and power distribution.
• Perform static timing analysis (STA), analyze timing reports, and implement timing ECOs using tools such as Tempus and Tempus ECO, or equivalent industry‑standard tools.
• Collaborate with RTL, Analog, DFT, Packaging, CAD, and EDA teams to resolve implementation issues and improve overall design convergence.
• Run and debug back‑end signoff checks, including power integrity, IR/EM analysis, and physical verification.
• Develop automation scripts using TCL, Python, Bash, or Perl for QoR tracking, reporting, and flow efficiency.

Minimum Qualifications

• Bachelor’s or Master’s in Electrical Engineering or equivalent field
• 3+ years of PD experience in ASIC/SoC physical design and implementation in advanced CMOS tech nodes
• Proven hands-on experience with the full physical design flow at block and/or chip level PD
• Good understanding of various EDA tools and sign-off criteria and experience in scripting and automation such as Python, Perl, TCL, or Shell Scripts
• Good team player

Preferred Qualifications

• Hands-on experience in closing designs with high-speed, high-density, macro-dominant blocks
• Strong knowledge of static timing analysis, timing constraints, and timing ECO implementation
• Hands-on experience with functional equivalence checking and functional ECOs
• Solid fundamentals in identifying and debugging EM, IR, RC, and glitch-related issues
• Solid Fundamentals in power grid design and optimization

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.