Meet the Team

The Common Hardware Group (CHG) delivers silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#Cisco Silicon One) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Your Impact

We are seeking a highly motivated engineer to join CAD & Methodology Team. The candidate will play a critical role in ensuring that ASIC projects are fully enabled with vendor IPs, standard cells, and Process Design Kits (PDKs), working closely with both internal teams and external vendors to drive enablement and management of essential components.

Key Responsibilities:

• Develop the platform for IP/PDK installations
• Develop a platform for IP quality assurance
• Establish and maintain efficient IP management methodologies, including version control, qualification, and distribution.
• Collaborate with IP vendors and foundries to facilitate IP and PDK enablement for ASIC projects.
• Benchmarking of different vendor/technology IPs
• Manage the integration, validation, and release of vendor IPs and PDKs into the internal design environment.
• Execute custom cells characterization and model generation with quality validation.
• Work with CAD, methodology, and physical design teams to ensure seamless enablement of design collateral, automation flows, and tool infrastructure.
• Evaluate and debug foundry PDKs, technology files, and libraries, ensuring they meet design requirements and flow compatibility.
• Develop and maintain documentation and guidelines for IP and PDK usage, integration, and best practices.

Minimum Qualifications

• 6+ years of experience in physical design enablement, CAD with strong knowledge of ASIC design flows, physical design methodologies, and foundry processes.
• Hands-on experience with IP installation, PDK enablement, and technology file management.
• Familiarity with EDA tools such as Synopsys, Cadence, Siemens for physical design and verification.
• Proficiency in scripting languages such as Python, TCL for automation and experience working with foundry process nodes and PDK management.
• Strong analytical and problem-solving skills with attention to detail and excellent communication & collaboration skills to work effectively across multiple teams and vendors.

Preferred Qualifications

• Logic library characterization knowledge is a plus

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.