採用
必須スキル
Advanced Packaging
2.5D/3D Stacking
Heterogeneous Integration
Chip-on-Wafer
Wafer-to-Wafer Bonding
Silicon Interposers
Through-Silicon Vias
RDL Packaging
Flip-chip Bonding
Substrate Embedding
Dicing
Solder Reliability
Failure Analysis
Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.
Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.
Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.
Advanced Packaging Technologist & Lead
We are seeking an accomplished Advanced Packaging Technologist & Lead to drive the development, integration, and deployment of next‑generation semiconductor packaging technologies. This role is critical in architecting and implementing advanced, high‑performance, and high‑density packaging solutions supporting cutting‑edge compute, AI, and heterogeneous integration platforms.
Key Responsibilities
Advanced Packaging Architecture & Development
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Design and implement advanced semiconductor packaging technologies, including 2.5D/3D stacking, heterogeneous integration, high-bandwidth interconnects, and advanced power-delivery architectures.
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Lead R&D in **Chip-on-Wafer (CoW)**and Wafer-to-Wafer (W2W) bonding approaches for high-density integration.
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Develop and optimize solutions using silicon interposers,Through-Silicon Vias (TSVs), and multi‑layer RDL packaging to enable ultra‑high‑bandwidth and low‑latency connections.
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Engineer advanced packaging structures using low‑CTE substrates,FLEX interconnects, and organic or ceramic substrate technologies.
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Align internal architects and external partners to deliver manufacturable designs and steer our strategic technology direction.
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Leverage simulation-driven design to reduce hardware iteration cycles and ensure first-pass success in complex architectures.
Assembly, Materials, & Interconnect Technologies
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Drive technology innovation in advanced buildup substrates, including designs with and without embedded dies.
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Oversee flip-chip bonding processes using both solder balls and copper pillars.
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Lead development of substrate embedding for silicon dies, capacitors, passives, and other active components.
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Develop and refine advanced dicing methodologies (laser and mechanical saw) tailored for nanometer-class nodes.
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Select materials; solder alloys, underfills, thermal interface materials (TIMs), and other key materials that enable high performance, manufacturability, and reliability
Process Technology & Reliability
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Manage package-level and board-level qualification, ensuring robust performance across thermal, mechanical, and electrical stress conditions
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Lead analysis and improvements in solder reliability, including temperature cycling, electromigration (EM), and stress modeling.
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Oversee ultra-thin die handling and processing for fragile, high-performance devices.
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Drive backside metallization and RDL process development to support advanced packaging roadmaps.
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Lead failure analysis when a new design fails a stress test and pivot the team toward a solution.
Qualifications
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BS EE, MS EE or equivalent engineering discipline
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10+ years of experience in advanced packaging
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Highly preferred: working knowledge of simulation tools (i.e. Ansys, Cadence, Abaqus)
The base salary range for this position is $175,000 to $275,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.
Why Join Cerebras
People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:
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Build a breakthrough AI platform beyond the constraints of the GPU.
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Publish and open source their cutting-edge AI research.
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Work on one of the fastest AI supercomputers in the world.
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Enjoy job stability with startup vitality.
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Our simple, non-corporate work culture that respects individual beliefs.
Read our blog: Five Reasons to Join Cerebras in 2026.
Apply today and become part of the forefront of groundbreaking advancements in AI!
*Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. **We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies.*We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.
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Cerebrasについて

Cerebras
Series F+Cerebras Systems Inc. is an American artificial intelligence (AI) company with offices in Sunnyvale, San Diego, Toronto, and Bangalore, India. Cerebras builds computer systems for complex AI deep learning applications.
201-500
従業員数
Sunnyvale
本社所在地
$4.1B
企業価値
レビュー
4.0
10件のレビュー
ワークライフバランス
2.8
報酬
4.2
企業文化
4.1
キャリア
4.3
経営陣
3.5
72%
友人に勧める
良い点
Innovative and cutting-edge technology
Supportive and collaborative team environment
Good compensation and benefits
改善点
Work-life balance challenges
High workload and expectations
Fast-paced and stressful environment
給与レンジ
33件のデータ
Mid/L4
Mid/L4 · Manufacturing Engineer
1件のレポート
$165,456
年収総額
基本給
$143,874
ストック
-
ボーナス
-
$165,456
$165,456
面接体験
50件の面接
難易度
3.9
/ 5
期間
21-35週間
内定率
23%
体験
ポジティブ 72%
普通 9%
ネガティブ 19%
面接プロセス
1
Recruiter Screen
2
ML Coding
3
ML System Design
4
Research Discussion
5
Team Interviews
よくある質問
ML fundamentals
Design an ML system
Research paper discussion
Statistical concepts
ニュース&話題
Nvidia Stock Faces a $20 Billion AI Chip Test as Cerebras Heads for IPO - TechStock²
TechStock²
News
·
3d ago
U.S. IPO Weekly Recap: IPO Calendar Heats Up As AI Chipmaker Cerebras Rejoins The Public Pipeline - Seeking Alpha
Seeking Alpha
News
·
3d ago
Nvidia Rival Cerebras Files For IPO After Scrapping Plans Last Year - Amazon.com (NASDAQ:AMZN), Barclays - Benzinga
Benzinga
News
·
3d ago
AI Chipmaker Cerebras Systems Files Publicly for US IPO - MENA Fintech Association
MENA Fintech Association
News
·
4d ago