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职位Cerebras

Advanced Packaging Technologist & Lead

Cerebras

Advanced Packaging Technologist & Lead

Cerebras

Sunnyvale, CA

·

On-site

·

Full-time

·

1mo ago

薪酬

$175,000 - $275,000

必备技能

Advanced Packaging

2.5D/3D Stacking

Heterogeneous Integration

Chip-on-Wafer

Wafer-to-Wafer Bonding

Silicon Interposers

Through-Silicon Vias

RDL Packaging

Flip-chip Bonding

Substrate Embedding

Dicing

Solder Reliability

Failure Analysis

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.

Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Advanced Packaging Technologist & Lead

We are seeking an accomplished Advanced Packaging Technologist & Lead to drive the development, integration, and deployment of next‑generation semiconductor packaging technologies. This role is critical in architecting and implementing advanced, high‑performance, and high‑density packaging solutions supporting cutting‑edge compute, AI, and heterogeneous integration platforms.

Key Responsibilities

Advanced Packaging Architecture & Development

  • Design and implement advanced semiconductor packaging technologies, including 2.5D/3D stacking, heterogeneous integration, high-bandwidth interconnects, and advanced power-delivery architectures.

  • Lead R&D in **Chip-on-Wafer (CoW)**and Wafer-to-Wafer (W2W) bonding approaches for high-density integration.

  • Develop and optimize solutions using silicon interposers,Through-Silicon Vias (TSVs), and multi‑layer RDL packaging to enable ultra‑high‑bandwidth and low‑latency connections.

  • Engineer advanced packaging structures using low‑CTE substrates,FLEX interconnects, and organic or ceramic substrate technologies.

  • Align internal architects and external partners to deliver manufacturable designs and steer our strategic technology direction.

  • Leverage simulation-driven design to reduce hardware iteration cycles and ensure first-pass success in complex architectures.

Assembly, Materials, & Interconnect Technologies

  • Drive technology innovation in advanced buildup substrates, including designs with and without embedded dies.

  • Oversee flip-chip bonding processes using both solder balls and copper pillars.

  • Lead development of substrate embedding for silicon dies, capacitors, passives, and other active components.

  • Develop and refine advanced dicing methodologies (laser and mechanical saw) tailored for nanometer-class nodes.

  • Select materials; solder alloys, underfills, thermal interface materials (TIMs), and other key materials that enable high performance, manufacturability, and reliability

Process Technology & Reliability

  • Manage package-level and board-level qualification, ensuring robust performance across thermal, mechanical, and electrical stress conditions

  • Lead analysis and improvements in solder reliability, including temperature cycling, electromigration (EM), and stress modeling.

  • Oversee ultra-thin die handling and processing for fragile, high-performance devices.

  • Drive backside metallization and RDL process development to support advanced packaging roadmaps.

  • Lead failure analysis when a new design fails a stress test and pivot the team toward a solution.

Qualifications

  • BS EE, MS EE or equivalent engineering discipline

  • 10+ years of experience in advanced packaging

  • Highly preferred: working knowledge of simulation tools (i.e. Ansys, Cadence, Abaqus)

The base salary range for this position is $175,000 to $275,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Why Join Cerebras

People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:

  • Build a breakthrough AI platform beyond the constraints of the GPU.

  • Publish and open source their cutting-edge AI research.

  • Work on one of the fastest AI supercomputers in the world.

  • Enjoy job stability with startup vitality.

  • Our simple, non-corporate work culture that respects individual beliefs.

Read our blog: Five Reasons to Join Cerebras in 2026.

Apply today and become part of the forefront of groundbreaking advancements in AI!

*Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. **We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies.*We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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关于Cerebras

Cerebras

Cerebras

Series F+

Cerebras Systems Inc. is an American artificial intelligence (AI) company with offices in Sunnyvale, San Diego, Toronto, and Bangalore, India. Cerebras builds computer systems for complex AI deep learning applications.

201-500

员工数

Sunnyvale

总部位置

$4.1B

企业估值

评价

4.0

10条评价

工作生活平衡

2.8

薪酬

4.2

企业文化

4.1

职业发展

4.3

管理层

3.5

72%

推荐给朋友

优点

Innovative and cutting-edge technology

Supportive and collaborative team environment

Good compensation and benefits

缺点

Work-life balance challenges

High workload and expectations

Fast-paced and stressful environment

薪资范围

33个数据点

Mid/L4

Mid/L4 · Manufacturing Engineer

1份报告

$165,456

年薪总额

基本工资

$143,874

股票

-

奖金

-

$165,456

$165,456

面试经验

50次面试

难度

3.9

/ 5

时长

21-35周

录用率

23%

体验

正面 72%

中性 9%

负面 19%

面试流程

1

Recruiter Screen

2

ML Coding

3

ML System Design

4

Research Discussion

5

Team Interviews

常见问题

ML fundamentals

Design an ML system

Research paper discussion

Statistical concepts