Jobs
Benefits & Perks
•401(k)
•Equity
•Healthcare
•Paid vacation
•Paid holidays
•401k
•Equity
•Healthcare
Required Skills
Python
Distributed systems
Dask
Data engineering
High-performance I/O
C interop
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
About the Role:
We're building a next-generation distributed transistor-level electromigration and IR drop analysis tool. Our team has strong expertise in numerical solvers and circuit simulation algorithms. We need an experienced distributed systems engineer to design the scalable data processing infrastructure for handling massive circuit designs across distributed computing resources.
What You'll Build
Architect and develop the core distributed infrastructure for a Python-based platform orchestrating high-performance C solvers, focusing on:
Data Pipeline & I/O Management
- Efficient ingestion pipelines for large-scale netlists and simulation data
- High-performance I/O for multi-TB circuit databases
- Serialization/deserialization layers bridging Python and C components
- Streaming results from distributed solver instances
Job Orchestration & Workflow
- Task distribution architecture with fault-tolerant scheduling for long-running simulations
- Resource management and load balancing across compute clusters
- Monitoring and observability for distributed workflows
- Optimization of task granularity and dependency management
Visualization & Analytics
- Scalable visualization for multi-dimensional TB-scale simulation results
- Interactive data exploration and optimization techniques (downsampling, LOD, progressive rendering)
Required Expertise
Distributed Systems
- 5 years building production distributed systems with Python
- Deep experience with Dask Distributed or similar frameworks (Spark, Ray, Celery)
- Strong grasp of distributed computing patterns, data locality, and fault tolerance
Data Engineering
- Expertise in high-performance I/O (HDF5, Parquet, Arrow, columnar formats)
- Data partitioning strategies, memory-mapped files, zero-copy techniques, streaming patterns
- Python/C interop (pybind11, Cython, ctypes)
Big Data Visualization
- Experience with large-scale scientific/engineering visualization systems
Nice to Have
- Background in EDA, VLSI, semiconductor design, or computational engineering
- HPC experience with job schedulers (Slurm, PBS, LSF)
- GPU acceleration knowledge
- Familiarity with modern languages, tools (Go, Plotly, Bokeh, Holoviews, Datashader)
- Open-source distributed computing contributions
Why Join Us
We bring strong expertise in numerical methods and circuit analysis algorithms, well-defined solver interfaces, and a clear technical vision. You'll build greenfield distributed infrastructure with modern tools, designing the scalable foundation that makes advanced analysis capabilities accessible to chip design engineers.
Ideal Candidate
You're a systems thinker excited about data pipeline architecture and production-scale distributed systems. You understand orchestrating heterogeneous workloads and designing elegant abstractions for distributed computing. You prioritize observability, fault tolerance, and user experience alongside performance.
No circuit simulation expertise needed—that's our strength. We need your expertise building scalable, reliable infrastructure.
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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About Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
Employees
San Jose
Headquarters
Reviews
3.3
7 reviews
Work Life Balance
2.0
Compensation
2.5
Culture
1.8
Career
2.0
Management
1.5
15%
Recommend to a Friend
Pros
Built strong client relationships
Useful for repetitive tasks
Employment opportunities
Cons
Poor management and micromanagement
Lack of career growth opportunities
Technical architecture and code quality issues
Salary Ranges
65 data points
Junior/L3
Junior/L3 · Data Analyst
1 reports
$91,103
total / year
Base
$85,276
Stock
-
Bonus
$5,827
$59,612
$139,984
Interview Experience
1 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
Common Questions
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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