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职位Cadence

Lead FrontEnd Methodology Engineer

Cadence

Lead FrontEnd Methodology Engineer

Cadence

BANGALORE

·

On-site

·

Full-time

·

2mo ago

福利待遇

Equity

Healthcare

Parental Leave

Flexible Hours

必备技能

PostgreSQL

React

JavaScript

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The candidate will have responsibilities to maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms, some in the Amazon and IBM clouds and some on-premise. The candidate will also have responsibilities in managing/monitoring regression trends, automating error/defect reporting, and supporting users in various server farms.

The candidate will have responsibilities to maintain/upgrade infrastructure/automation for RTL development and design-verification teams at multiple locations using multiple server farms, some in the Amazon and IBM clouds and some on-premise. The candidate will also have responsibilities in managing/monitoring regression trends, automating error/defect reporting, and supporting users in various server farms.

We’re looking for a candidate who has the following skillsets:

  • Extensive knowledge of Perl and Python
  • Knowledge of dependency-checking via make, SCons
  • LSF or other batch-queuing system (e.g. Grid, PBS, Open Lava), and script integration
  • Using REST API (e.g. Jenkins, Jira) from Perl, Python
  • Migrating scripts, script-libraries to different Linux OS releases
  • Knowledge of SQL, relational database engines like MariaDB or PSQL, and integration with Perl/Python
  • Knowledge of web technologies: Basic Apache setup, PHP, Javascript/Jquery, RSS automation

These skillsets and knowledge would also be desirable:

  • BS/MS - Electrical / Computer Engineering.
  • At least 7 years of of relevant experience.
  • Updating/debugging TCL code embedded in a variety of tools, such as simulator, waveform-viewer, formal verification, in-house interpreter, etc.
  • Knowledge of Verilog, System Verilog testbenches; some familiarity with methodologies like OVM or UVM; incorporate DPI or PLI models
  • Some IT knowledge: NFS, memory/CPU profiling, NIS/DNS/LDAP, SMTP, syslog, cron, etc
  • Jenkins install/configuration/management
  • Module-files and modulecmd to manage tools and tool-versions
  • Cloud deployment/maintenance: Amazon Web Services, MS Azure, IBM Cloud
  • Experience with revision control like git or GitHub
  • The position is based in Austin/San Jose/Bangalore (India)

We’re doing work that matters. Help us solve what others can’t.

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

4.0

10条评价

工作生活平衡

4.2

薪酬

2.8

企业文化

4.1

职业发展

3.2

管理层

3.4

72%

推荐给朋友

优点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

缺点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

薪资范围

58个数据点

Mid/L4

Mid/L4 · Design Engineer

6份报告

$139,837

年薪总额

基本工资

$124,197

股票

-

奖金

-

$110,434

$186,828

面试经验

1次面试

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving