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职位Cadence

Principal Product Engineer

Cadence

Principal Product Engineer

Cadence

CORK 01

·

On-site

·

Full-time

·

2mo ago

薪酬

$136,500 - $253,500

福利待遇

Equity

Healthcare

Parental Leave

Flexible Hours

必备技能

TypeScript

React

PostgreSQL

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence.   The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of  technical place and route expertise to Cadence customers and to R&D.

You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.
You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.
You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach.
You are an excellent communicator.

Position Responsibilities:

Support Cadence products in the Digital and Signoff team.
Track and debug customer issues and work with R&D and release team on issue resolution.
Run design benchmarks and develop flows and solutions.

Position Requirements:

MS in EE with 8 years of experience in Digital Implementation, either as a design engineer or as a product engineer
Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff.
Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.
Exposure to, and solid understanding of, hierarchical design methodologies and low power design
Energetic team player with a passion for problem solving
Strong analysis skills with a track record to prove it
Strong communication skills (verbal and written)
Automation skills using Perl, Tcl and shell scripting

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

4.0

10条评价

工作生活平衡

4.2

薪酬

2.8

企业文化

4.1

职业发展

3.2

管理层

3.4

72%

推荐给朋友

优点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

缺点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

薪资范围

58个数据点

Mid/L4

Mid/L4 · Design Engineer

6份报告

$139,837

年薪总额

基本工资

$124,197

股票

-

奖金

-

$110,434

$186,828

面试经验

1次面试

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving