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职位Cadence

Sr. Principal Product Engineer (EMIR / PDN Analysis & Power Integrity)

Cadence

Sr. Principal Product Engineer (EMIR / PDN Analysis & Power Integrity)

Cadence

SAN JOSE

·

On-site

·

Full-time

·

1mo ago

必备技能

Python

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Job Responsibilities• Be part of the product engineering team working on Power Noise Reliability analysis platform within Multiphysics Systems BU at Cadence.

  • Build domain expertise in power integrity , 3DIC analysis & optimization , Industry’s first AI driven IR mitigation & fixing methodology , electrothermal optimization for digital designs.

  • Work closely with R&D to facilitate the development of these methodologies and flows.

  • Responsibilities also including supporting strategic customers and functional product engineering driving solutions in the Multiphysics space.

  • Minimum Qualifications

  • Bachelor’s Degree in Electrical / Electronics / Electronics and Communication / VLSI Engineering with 8+ years related experience.

  • Experience and Technical Skills required

  • Experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation.

  • Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design.

  • Debugging of Low power and multiple power domain analysis for chip power integrity sign-off.

  • Experience with 3DIC design and methodologies is a plus.

  • Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.

  • Ability to solve interface level problems emanating from IC Implementation side and System analysis side.

  • Ability to debug Timing and thermal issues in relation to IR and EM is a plus.

  • Knowledge on TCL, Perl or Python scripting.

  • Behavioral skills required

  • Must possess strong written, verbal and presentation skills.

  • Ability to establish a close working relationship with both customer peers and management.

  • Explore what’s possible to get the job done, including creative use of unconventional solutions.

  • Work effectively across functions and geographies.

  • Push to raise the bar while always operating with integrity.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

4.0

10条评价

工作生活平衡

4.2

薪酬

2.8

企业文化

4.1

职业发展

3.2

管理层

3.4

72%

推荐给朋友

优点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

缺点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

薪资范围

58个数据点

Junior/L3

Junior/L3 · Data Analyst

1份报告

$91,103

年薪总额

基本工资

$85,276

股票

-

奖金

$5,827

$59,612

$139,984

面试经验

1次面试

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving