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Sr. Principal Product Engineer (EMIR / PDN Analysis & Power Integrity)
SAN JOSE
·
On-site
·
Full-time
·
1mo ago
必須スキル
Python
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
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Job Responsibilities• Be part of the product engineering team working on Power Noise Reliability analysis platform within Multiphysics Systems BU at Cadence.
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Build domain expertise in power integrity , 3DIC analysis & optimization , Industry’s first AI driven IR mitigation & fixing methodology , electrothermal optimization for digital designs.
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Work closely with R&D to facilitate the development of these methodologies and flows.
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Responsibilities also including supporting strategic customers and functional product engineering driving solutions in the Multiphysics space.
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Minimum Qualifications
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Bachelor’s Degree in Electrical / Electronics / Electronics and Communication / VLSI Engineering with 8+ years related experience.
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Experience and Technical Skills required
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Experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physical implementation.
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Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design.
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Debugging of Low power and multiple power domain analysis for chip power integrity sign-off.
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Experience with 3DIC design and methodologies is a plus.
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Must have excellent debugging skills and ability to separate out the critical issues from trivial ones.
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Ability to solve interface level problems emanating from IC Implementation side and System analysis side.
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Ability to debug Timing and thermal issues in relation to IR and EM is a plus.
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Knowledge on TCL, Perl or Python scripting.
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Behavioral skills required
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Must possess strong written, verbal and presentation skills.
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Ability to establish a close working relationship with both customer peers and management.
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Explore what’s possible to get the job done, including creative use of unconventional solutions.
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Work effectively across functions and geographies.
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Push to raise the bar while always operating with integrity.
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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Cadenceについて

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
従業員数
San Jose
本社所在地
$8.5B
企業価値
レビュー
4.0
10件のレビュー
ワークライフバランス
4.2
報酬
2.8
企業文化
4.1
キャリア
3.2
経営陣
3.4
72%
友人に勧める
良い点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
改善点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
給与レンジ
58件のデータ
Junior/L3
Junior/L3 · Data Analyst
1件のレポート
$91,103
年収総額
基本給
$85,276
ストック
-
ボーナス
$5,827
$59,612
$139,984
面接体験
1件の面接
難易度
3.0
/ 5
期間
14-28週間
面接プロセス
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
よくある質問
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
ニュース&話題
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