Lead Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

JOB Description:

RESPONSIBILITIES:

• Development of test plans, tests, and verification infrastructure for complex IP’s/sub-systems/SOC’s.
• Creation of verification environment using UVM methodology or equivalent.
• Construction of reusable bus functional models, monitors, checkers, and scoreboards.
• Leading functional coverage verification closure.

SKILL SETS:

• BTech/ MTech in Engineering.

Or Equivalent or Relavent:

• 4-7 years of VLSI industry experience in Verification.

Equivalent or Relavent:

• Expertise in SoC level verification and IP/Subsystem validation.
• Proficiency in developing test bench/testbench components, test plans, test cases, functional coverage, assertions, and coverage analysis.
• Strong knowledge of UVM, SV.
• Familiarity with protocols like UCIe, PCIe, DDR, USB, AMBA.
• Skilled individual contributor and mentor with exceptional debug and problem-solving abilities.
• Extensive experience in the verification cycle for complex SOCs.

We’re doing work that matters. Help us solve what others can’t.