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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description:
Join our elite Application Engineering team for verification to work closely with the best AEs, PEs and R&D in EDA at a company listed in Fortune magazine and Great Place to Work as one of the 2025 World's Best Workplaces™ for the sixth time!
As an integral member of the North America Field Applications Engineering (AE) Team, you will work directly with industry leading semiconductor and system companies to deploy Cadence’s market leading Emulation and FPGA prototyping platforms, Palladium and Protium. In this customer facing role you will provide the front line technical support in the pre and post-sales process and will work with team members to come up with innovative solutions to address our customers’ most challenging problems in emulation and prototyping.
As part of the team, you will develop customer specific emulation and prototyping requirements, including advanced acceleration component development, methodology support, and operation and maintenance of Cadence’s emulation and prototyping tools and services. You will support technical evaluations and benchmark development for Cadence’s market leading tools such as Palladium acceleration and emulation platform and Protium prototyping platform. You will create and conduct technical presentations and product demonstrations for customers.
Key Responsibilities:
- Establish technical credibility and rapport with the customer
- Work closely with an experienced team to become the go-to expert for technical inquiries and support for emulation and prototyping
- Become part of a team that provides in-depth technical assistance in collaboration with R&D to help support advanced acceleration/emulation/prototyping flows to secure design wins
- Champion the customer needs and work with R&D and marketing to develop competitive and creative technical solutions
- Learn the competitive landscape and continuously work on differentiating Cadence’s solutions
- Write technical product literature such as application notes and technical articles
Requirements Minimum:
Lab or internship experience leveraging hands on experience with FPGA prototyping including compilation, debug and performance optimization on FPGA prototyping platforms (Protium or HAPS is a plus)
Experience with hardware accelerators and emulators is a plus
Lab or internship experience with bring up, debug, chipscope and instrument usage
Education or experience in Verilog and Systemverilog:
Knowledge of design fundamentals such as architecture, micro-architecture, HDLs and Synthesis and timing
Also;
M.Sc. or B.Sc. degree in Computer Science, Engineering, or related field
Good understanding and knowledge of Object Oriented Programming and experience in one such programming language such as C++, Java, Python or Systemverilog
Knowledge of Linux/Unix platforms and scripting languages such as Perl, TCL, Python
Strong verbal and written communication skills in English
Self-motivated and strong teamwork skills
Strong problem solving skills
The annual salary range for San Jose, CA is $ 84,000 to $156,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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Cadenceについて

Cadence
PublicCadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.
5,001-10,000
従業員数
San Jose
本社所在地
$8.5B
企業価値
レビュー
4.0
10件のレビュー
ワークライフバランス
4.2
報酬
2.8
企業文化
4.1
キャリア
3.2
経営陣
3.4
72%
友人に勧める
良い点
Good work-life balance and flexible hours
Supportive and collaborative team environment
Good benefits and stable company
改善点
Below market compensation and pay
Limited growth and advancement opportunities
Heavy workload and long hours during peak times
給与レンジ
66件のデータ
Junior/L3
Junior/L3 · Data Analyst
1件のレポート
$91,103
年収総額
基本給
$85,276
ストック
-
ボーナス
$5,827
$59,612
$139,984
面接体験
1件の面接
難易度
3.0
/ 5
期間
14-28週間
面接プロセス
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
よくある質問
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
ニュース&話題
Cadence Design Systems Inc. stock outperforms competitors on strong trading day - MarketWatch
MarketWatch
News
·
2d ago
Album Review: Forager by Cadence Weapon & Junia-T - Shatter the Standards
Shatter the Standards
News
·
2d ago
Cadence Collaborates with TSMC to Accelerate Design of Next-Gen AI Silicon - HPCwire
HPCwire
News
·
2d ago
Cadence Design Systems Targets Faster Chip Design Cycles To Keep Pace With AI - Benzinga
Benzinga
News
·
2d ago