At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

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• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
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• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
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You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day

Job Description:

JOB Role:

Senior Principal Design Engineer:

The responsibility entails leading pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation efforts primarily on Cadence's High Speed SERDES Test chips, ie, activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc.

What we are looking for in potential candidates is listed below.

Minimum Qualifications:

• 10-15 years (with Btech) or 8-13 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation

• Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc

• Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc

Preferred Qualifications:

• Experience managing small teams (at least 2 members and above) is a strong plus

• Experience leading the complete post silicon validation efforts for at least one full project

• 1-2 years of experience in Analog, PLL,FPGA Design, PCB schematic and layout design & Prototyping is a strong plus

• Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug.

• Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL

• Experience conducting hiring interviews and mentoring new hires

• Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.

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