招聘
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Job Description
The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post–sales activities at advanced nodes for Cadence Digital IC products.
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Key Responsibilities
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Provide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff
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Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
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Conduct technical presentations and product demonstrations
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Drive technical evaluations/benchmarks to success
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Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements
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Drive adoption and proliferation of Cadence tools and technologies
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Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
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Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements
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Provide technical support, when developing business case for process improvement projects.
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Provide mentorship to junior engineers
Job Requirements
- Requires a BS or MS or PhD in EE with/or 12-15 years industry related experience in design and EDA (Digital Implementation/Signoff)
- Understands ASIC Design implementation process and steps
- Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler)
- Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler)
- Experience with EDA tools in the IC digital implementation & signoff flows (STA tools)
- Strong STA and SDC debugging abilities are required.
- Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus.
- Automation skills using Perl, Tcl and shell scripting essential
- Strong analytical & analysis skills covering digital implementation is critical.
- Proven track record and experience working in a fast paced environment
- Excellent customer interaction & presentation skills
The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
缺点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
薪资范围
58个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
新闻动态
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