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채용Cadence

Senior AE Group Director

Cadence

Senior AE Group Director

Cadence

SAN JOSE

·

On-site

·

Full-time

·

1mo ago

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Sr. Group Director – Memory and Serdes Applications

Position Overview

Cadence is seeking a motivated, detail-oriented, and creative leader to join the North America IP Sales team as the Senior Director of Applications Engineering for our Design IP portfolio. The ideal candidate is an experienced High-Speed Interface Technologist who excels at leading multiple teams of skilled engineers and collaborating with customers to develop solutions for their System/ASIC/SoC designs using the Cadence Serdes and memory IP portfolio. This is a pre-sales role, well-suited for someone with System/ASIC/SoC design experience, strong interpersonal and communication skills, and a commitment to ensuring customer success. The position offers the opportunity to work across various market segments, including AI, Cloud, Networking, and Storage, as well as designs, foundries, and leading-edge processes. The successful candidate will build credibility by addressing the most challenging high-speed interface and memory problems.

Key Responsibilities

  • Lead and mentor a high-performing team of senior application engineers focused on technical presales for high-speed interface PHYs and controllers.
  • Develop strategies to secure complex bundle IP and services deals that encompass memory, Serdes, and foundation IPs.
  • Establish the infrastructure and methodology necessary to integrate new IP acquisitions and drive efficiency improvements using AI.
  • Develop customer solutions by leveraging the broad Cadence IP portfolio.
  • Collaborate with sales and marketing teams to identify and understand customers’ technical and business challenges.
  • Educate customers on how Cadence's IP products address their requirements and assist them in evaluating the IP, with support from product R&D teams.
  • Influence the IP product development roadmap by communicating customer needs to product R&D teams.
  • Stay informed about industry trends and protocol evolutions at JEDEC, PCI-SIG, and other standards bodies.
  • Manage and support customer engagements through on-site or remote technical interactions, including providing demos, supporting evaluations, resolving technical issues, addressing competitive challenges, and regularly communicating status across cross-functional teams.

Qualifications and Experience

  • MSEE with 20+ years of relevant experience, or PhD with 15+ years of relevant experience.
  • Management experience leading a highly technical team.
  • Previous experience in selecting, using, designing, or supporting PHY and controller interface IP, internally or externally.
  • Understanding of the latest SoC architectures and system-level design practices for market segments such as AI, HPC, mobile, storage, automotive, networking, and IoT, with a particular focus on IP requirements.
  • Prior experience and knowledge of one or more interface, memory, and connectivity protocols, including DDR, LPDDR, HBM, PCIe, CXL, UCIe, and Ethernet.
  • Familiarity with state-of-the-art SoC design implementation and development flow, including RTL design, synthesis and static timing analysis, physical design flow, testbench creation and simulation, some exposure to analog/mixed-signal design and verification flows, and basic knowledge of foundry, package, and PCB design flows and technologies.
  • Prior IP or SoC design experience is highly desirable.
  • Ability to understand and communicate complex technical requirements, challenges, and solutions clearly in both verbal and written formats.
  • Proven ability to organize, conduct, and coordinate meetings involving multiple internal and external teams.
  • Willingness to travel approximately 10% of the time to visit customers, sales teams, and engineering locations.

The annual salary range for California is $187,600 to $348,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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Cadence 소개

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

직원 수

San Jose

본사 위치

$8.5B

기업 가치

리뷰

4.0

10개 리뷰

워라밸

4.2

보상

2.8

문화

4.1

커리어

3.2

경영진

3.4

72%

친구에게 추천

장점

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

단점

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

연봉 정보

58개 데이터

Director

Director · AE Director

1개 리포트

$231,621

총 연봉

기본급

$201,323

주식

-

보너스

-

$231,621

$231,621

면접 경험

1개 면접

난이도

3.0

/ 5

소요 기간

14-28주

면접 과정

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

자주 나오는 질문

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving