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Cadence

Intern

Cadence

CORK 01

·

On-site

·

Internship

·

2mo ago

必备技能

Digital Design

Verilog

Tcl

Perl

Shell scripting

RTL design

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality.

This strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the world’s most innovative companies, delivering extraordinary electronic products—from chips to boards to systems—for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health. Join us and be part of a culture that values innovation, collaboration, and customer success.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Design Engineering Intern

Location: Cork

Job Overview: The Cadence Tensilica CPU Processor Team is seeing rapid adoption of our industry leading processor cores and DSP's. Our configurable and extensible processor cores are poised to meet the demands of intelligent IoT Devices at the edge of ML/AI Applications. We are already empowering many of the top chip and system companies with our Audio, Speech, AR/VR, ADAS, Vision and Imaging applications being driven with our processor cores. Today Cadence is shipping an astounding 8 billion processor cores annually and expanding into intelligent system design and development.

Cadence Tensilica CPU Processor Team is hiring engineering interns to join our R&D team in Cork, Ireland. This is an amazing opportunity to work as a Graduate Engineer at a world leader in computational software, semiconductor design IP, and system verification hardware.  Our customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

Come be part of this great Processor team where you can make an impact that is visible.

Job Responsibilities: Perform as a member of the Logic Design Team for Xtensa processors. Responsible for the RTL implementation of microprocessor cores, multiprocessor sub-systems and their peripherals. Implement the micro-architecture in Verilog RTL, simulate and debug its functions and run synthesis, place & route and other Electronic Design Automation scripts to meet timing, area, and power goals. Assist with developing test plans; writing functional diagnostics; debugging failures; and analyzing coverage information. Work closely with various Design Verification and Electronic Design Automation teams.

Position Requirements: •  Pursuing Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a similar major.

  • Deep understanding of Digital Design Fundamentals

  • Excellent automation skills using Tcl, Perl, shell scripting

  • Excellent oral and written communications skills

  • Exposure to design automation tools is a plus

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

We’re doing work that matters. Help us solve what others can’t.

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

4.0

10条评价

工作生活平衡

4.2

薪酬

2.8

企业文化

4.1

职业发展

3.2

管理层

3.4

72%

推荐给朋友

优点

Good work-life balance and flexible hours

Supportive and collaborative team environment

Good benefits and stable company

缺点

Below market compensation and pay

Limited growth and advancement opportunities

Heavy workload and long hours during peak times

薪资范围

66个数据点

Junior/L3

Mid/L4

Senior/L5

Intern

Junior/L3 · Associate

10份报告

$109,936

年薪总额

基本工资

$97,510

股票

-

奖金

$12,426

$64,329

$189,193

面试经验

1次面试

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving