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Cadence
Cadence

Leading company in the technology industry

Lead Design Engineer

职能工程
级别Lead级
地点SAN JOSE
方式现场办公
类型全职
发布1周前
立即申请

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Lead Design Engineer – Roles & Responsibilities

  • Contribute to analog and AMS design activities for high‑speed memory interface PHYs, with strong hands‑on execution capability
  • Evaluate architecture models and feasibility studies to assess performance, power, area, and scalability trade‑offs
  • Support early architecture exploration by providing circuit‑level insight and validating architectural assumptions
  • Actively support silicon bring‑up, lab debug, and characterization, including root‑cause analysis of analog, AMS, and PHY‑level issues
  • Show willingness to jump into any technical domain that requires immediate attention to unblock teams or customers
  • Contribute to technical documentation by identifying gaps, proposing improvements, and supporting the creation of design documents and architecture support material
  • Act as a dependable technical contributor during critical phases such as silicon validation, and customer escalations
  • Apply AI‑based approaches to automate repetitive tasks, and enhance engineering productivity

Required Qualifications

  • M.S. degree in Electrical Engineering, Computer Engineering, or related field (required or strongly preferred)
  • Minimum 7 years of industry experience in analog / AMS design, memory PHYs, or high‑speed IO
  • Strong hands‑on experience with analog and AMS circuits
  • Solid background in DDR / LPDDR memory interfaces

The annual salary range for California is $114,800 to $213,200. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

10条评价

3.9

10条评价

工作生活平衡

3.8

薪酬

2.7

企业文化

4.2

职业发展

3.2

管理层

2.8

72%

推荐率

优点

Flexible work arrangements and remote options

Great company culture and collaborative team

Good benefits and job security

缺点

Below average compensation and salary

High workload and overwhelming at times

Limited career advancement opportunities

薪资范围

75个数据点

Junior/L3

Junior/L3 · Data Analyst

1份报告

$91,103

年薪总额

基本工资

$85,276

股票

-

奖金

$5,827

$59,612

$139,984

面试评价

1条评价

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving