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トレンド企業

トレンド企業

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求人Cadence

SI/PI for 3DIC Sr Principle Solutions Engineer

Cadence

SI/PI for 3DIC Sr Principle Solutions Engineer

Cadence

No Seat Req United States; SAN JOSE

·

On-site

·

Full-time

·

4w ago

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This position involves defining and leading the development of advanced packaging and 3DIC analysis flows for foundry and customer solutions. The candidate will have expert knowledge of the Cadence toolset and/or equivalent competitor toolsets in the context of multiple flows including high-speed signal design, power design, signal integrity, power integrity and definition of electrical constraints. Design experience and industry knowledge of one of Signal, Power, and Thermal analysis associated with IC, package, or PCB design is required .

The candidate needs to have the ability to analyze the customer's environment and evaluate appropriate solutions. Be knowledgeable and aware of competitive technologies. Anticipates technical issues and develops creative solutions before they become a problem. Takes technical lead on a wide range of projects. Ability to understand high-speed, high-performance signal and power integrity-related issues, and work with peers and other business groups.  Able to communicate effectively with Cadence R&D, Product Engineering, Marketing and with customers. Understands customer success criteria and is committed to ensuring customer success.

Position requires:

  • Bachelor’s degree (Masters preferred) in Electrical or Electronics Engineering with
  • Minimum 15 years experience with Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF related to Package and PCB Design is required
  • 5+ years experience with Cadence SI/PI tools Allegro platform tools including: Sigrity, Clarity, PCB Editor, ICP preferred
  • Strong knowledge of advanced packaging concepts
  • Strong knowledge of 2.5D, 3DIC and stacked die technologies
  • Understanding of chip level CMOS design concepts desired
  • Strong customer-facing communication and problem-solving skills
  • Strong personal drive for continuous learning and expanding professional skill sets
  • Excellent verbal and written communication skills

The annual salary range for California is $143,500 to $266,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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0

応募クリック数

0

模擬応募者数

0

スクラップ

0

Cadenceについて

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

従業員数

San Jose

本社所在地

$8.5B

企業価値

レビュー

4.0

10件のレビュー

ワークライフバランス

4.2

報酬

2.8

企業文化

4.1

キャリア

3.2

経営陣

3.4

72%

友人に勧める

良い点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

改善点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

給与レンジ

58件のデータ

Junior/L3

Junior/L3 · Data Analyst

1件のレポート

$91,103

年収総額

基本給

$85,276

ストック

-

ボーナス

$5,827

$59,612

$139,984

面接体験

1件の面接

難易度

3.0

/ 5

期間

14-28週間

面接プロセス

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

よくある質問

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving