refresh

트렌딩 기업

트렌딩

채용

JobsCadence

Senior Principal Software Engineer

Cadence

Senior Principal Software Engineer

Cadence

SAN JOSE

·

On-site

·

Full-time

·

4d ago

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join our R&D team building next‑gen **Accelerated Verification IP (AVIP)**and Virtual Bridge solutions for high‑performance IO and memory coherence. You’ll architect, implement, and productize PCIe Gen7 and CXL 2.0/3.x features across C++, UVM and virtualized system models that enable hardware, emulation, and hybrid platforms.

What you’ll do

  • Design and enhance PCIe/CXL AVIP (agents, monitors, scoreboards, sequencers, coverage, error injection).
  • Develop Virtual Bridge components that connect virtual platforms/emulators/FW to RTL (traffic modeling, performance, debug).
  • Own feature bring‑up for CXL.io / CXL.cache / CXL.mem, IDE/security, RAS, switching/fabric (CXL 3.x).
  • Deliver compliance and interoperability scenarios; drive customer escalations and cross‑team integration.

What you’ll need

  • BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience

  • Experience with PCIe and/or CXL design/verification, deep protocol‑layer knowledge (LTSSM, DLL/TLP, flow control, ordering).

  • Proficiency in VerilogRTL design and debug

  • Experience with emulation/acceleration or hybrid (virtual + RTL) flows; solid debug skills (waveforms, checkers, coverage).

Nice to have

  • PCIe Gen6/CXL 3.x fabric features (multi‑level switching, global fabric attach, pooling).
  • Performance modeling, QoS/traffic shaping; firmware/OS driver bring‑up exposure; compliance tools.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Total Views

0

Apply Clicks

0

Mock Applicants

0

Scraps

0

About Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

Employees

San Jose

Headquarters

Reviews

3.3

7 reviews

Work Life Balance

2.0

Compensation

2.5

Culture

1.8

Career

2.0

Management

1.5

15%

Recommend to a Friend

Pros

Built strong client relationships

Useful for repetitive tasks

Employment opportunities

Cons

Poor management and micromanagement

Lack of career growth opportunities

Technical architecture and code quality issues

Salary Ranges

65 data points

Junior/L3

Junior/L3 · Data Analyst

1 reports

$91,103

total / year

Base

$85,276

Stock

-

Bonus

$5,827

$59,612

$139,984

Interview Experience

1 interviews

Difficulty

3.0

/ 5

Duration

14-28 weeks

Interview Process

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

Common Questions

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving