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职位Cadence

Lead Solutions Engineer – Runset Enablement (Physical Verification)

Cadence

Lead Solutions Engineer – Runset Enablement (Physical Verification)

Cadence

AUSTIN

·

On-site

·

Full-time

·

2mo ago

福利待遇

Learning

Parental Leave

Healthcare

必备技能

TypeScript

JavaScript

PostgreSQL

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are seeking a Lead Solutions Engineer specializing in** runset enablement** to support advanced semiconductor technologies. This role is critical for timely delivery of physical verification solutions by providing full-time coverage in the U.S. time zone. You will lead development and validation of Pegasus** DRC and LVS runsets**, collaborate with R&D on CCRs, and enable customer adoption through robust automation and best practices.

Key Responsibilities

  • Lead development and validation of Pegasus DRC and LVS runsets for advanced nodes.
  • Architect automation frameworks for regression execution, issue detection, and validation reporting.
  • Collaborate with R&D to resolve CCRs, influence product roadmap, and implement performance improvements.
  • Provide technical enablement and support for customers on tool usage and advanced methodologies.
  • Mentor junior engineers and establish best practices for runset development and QA.
  • Work closely with internal teams to ensure timely delivery of verification solutions.

Qualifications

  • MS degree with 5+ years of experience or PhD with 3+ years in Electrical Engineering, Computer Science, or related field.
  • Strong understanding of semiconductor design and physical verification flows.

Experience and Technical Skills

  • Proven expertise in developing and validating DRC and LVS runsets for Pegasus or similar tools (Calibre, ICV, Assura).
  • Good-to-have: Experience with PERC and Fill runsets.
  • Deep knowledge of advanced process technologies and methodologies (Ground Rules, Smart Fill, ESD).
  • Proficiency in scripting languages (TCL, Python, Perl) and Linux/Unix environments.
  • Familiarity with chip fabrication processes and multi-die integration challenges.
  • Experience in automation frameworks for regression and validation.

Behavioral Skills

  • Strong leadership and mentoring capabilities.
  • Excellent written, verbal, and presentation skills.
  • Ability to influence cross-functional teams and drive strategic initiatives.
  • Innovative mindset to explore unconventional solutions and optimize workflows.
  • Operate with integrity and foster collaboration across global teams.

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.

We’re doing work that matters. Help us solve what others can’t.

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

4.0

10条评价

工作生活平衡

4.2

薪酬

2.8

企业文化

4.1

职业发展

3.2

管理层

3.4

72%

推荐给朋友

优点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

缺点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

薪资范围

58个数据点

Junior/L3

Junior/L3 · Data Analyst

1份报告

$91,103

年薪总额

基本工资

$85,276

股票

-

奖金

$5,827

$59,612

$139,984

面试经验

1次面试

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving