招聘
必备技能
MOS transistors
Physical verification
DRC
LVS
Parasitic extraction
IR Drop analysis
Electromigration
Tcl
Perl
Python
Communication
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Design Systems Inc. is looking for a motivated
Application Engineer II: Silicon Signoff and Verificationcandidate to work with us in Belo Horizonte, Brazil
**.At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.
As a
Senior Application Engineering:
- Silicon Signoff and Verification **member, you will be part of the **Silicon Signoff and Verification (SSV)team.
The SSV team works with the Quantus,Pegasus and Voltus platforms.
To understand more on what we do, you can visit here.
Job Description:
- Helping customers to adopt and proliferate our IC Signoff solutions
- Conducting technical presentations, technical training, and product demonstrations, including development of customized presentations
- Supporting technical evaluations and benchmarks
- Help R&D and product engineers develop competitive and creative technical solutions
Requirements:
- Complete Bachelors in Electrical, Electronics, System Engineering, computer science or related areas
- MOS transistors, Physical verification flows ( i.e.. DRC, LVS & FILL), Parasitic extraction flows, IR Drop/Electromigration tools, Physical verification rule writing.
- Excellent written and verbal communication skills
- Interest in learning new technologies
- Open to continued personal development to meet the evolving demands of the EDA industry
- Experience in scripting languages such as Tcl/Perl/Python is a must
- Team player with a positive attitude, willingness to offer and execute ideas and solutions to enhance processes within an evolving environment
Nice to have:
- Industry Physical Design experience
- Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking
- Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired
- Experience with advanced nodes
Additional Job Details:
- Employment category: CLT
- Employment term: 40 hours/week.
- Competitive benefits.
- Location: Av Contorno 5800, Belo Horizonte, Minas Gerais Brazil.
About Cadence Design Systems:
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
缺点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
薪资范围
58个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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