招聘
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Sr. Principal SI/PI Engineer
This is a unique opportunity to join the HPP IP R&D Group at Cadence Design Systems. We are looking for a Sr Principal SI/PI Engineer who will be a key contributor to our advanced high speed IP products. This is a hands-on technical position.
Main Job Tasks and Responsibilities:
- Work on test chip package design SI/PI optimization and verification.
- Work on evaluation board design optimization for best SI/PI performance.
- Provide extracted and measured channel models for chip designers in the R&D team.
- Help with package and PCB SI/PI design guidelines and customer support on SI/PI related inquiries.
- Review customer package and board designs and simulation results. Help with providing feedback to customers to ensure best possible performance of our IP in their ASIC.
- Work on link performance simulations using S-parameter channel models and IBIS-AMI behavioral models.
- Help with SI/PI related debug of test chips or customer ASICs in the lab.
Position Requirements:
- M.S. or Ph.D. Electrical Engineering (or similar degree)
- 3+ years of experience preferably working with high speed Ser Des and PHYs
- Good understanding of high speed Ser Des architecture
- Hands on lab experience with instruments like high speed oscilloscopes, TDRs, VNAs, spectrum analyzers, etc.
- Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave
- Experience with IBIS-AMI model simulations
- Experience with simulation result to lab measurement correlation
- Good understanding of PCB and FCBGA design rules and requirements
- Strong debugging and problem-solving skills
- Excellent communication and presentation skills to effectively communicate with both customers and internal stake holders
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance and flexible hours
Supportive and collaborative team environment
Good benefits and stable company
缺点
Below market compensation and pay
Limited growth and advancement opportunities
Heavy workload and long hours during peak times
薪资范围
66个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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