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职位Cadence

Lead Solutions Engineer

Cadence

Lead Solutions Engineer

Cadence

BANGALORE

·

On-site

·

Full-time

·

2mo ago

福利待遇

Equity

Parental Leave

Healthcare

必备技能

Python

React

PostgreSQL

Cadence

  • Verification Engineer

About the Role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We're doing work that matters. Help us solve what others can't.

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Responsibilities

  • Understand/review Design specification and develop verification strategy/Test plan/coverage plan
  • Development of constrained random verification environments and verification components
  • Writing tests/sequences/functional coverage/assertions to meet verification goals
  • Developing c-based test cases for SOC verification

Required Experience

  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development
  • System Verilog experience and experience with UVM based functional verification environment development
  • Good knowledge of verilog/vhdl/C/C++/Perl/Python
  • Expertise in AMBA protocols (AXI/AHB/APB)
  • Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols
  • Good handle on using one or more version control software
  • Good handle on using one or more load sharing software
  • Strong vocabulary, communication, organizational, planning, and presentation skills
  • Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment
  • Ability and desire to learn new methodologies, languages, protocols etc.
  • Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry
  • Self-motivated and willing take up additional responsibilities to contribute to team's success

Desirable Skills and Experience

  • Prior experience with Cadence tools and flows
  • Familiarity with ARM/CPU architectures
  • Experience in developing c-based test cases for SOC verification
  • Some experience with assembly language programming
  • Good knowledge of some of the protocols like UART, I2C, SPI, JTAG
  • Embedded C code development and debug
  • Formal Verification experience

Equal Opportunity

Cadence is committed to equal employment opportunity throughout all levels of the organization. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Accessibility and E-Verify

We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com.

Cadence participates in the E-Verify program in certain U.S. locations as required by law.

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

4.0

10条评价

工作生活平衡

4.2

薪酬

2.8

企业文化

4.1

职业发展

3.2

管理层

3.4

72%

推荐给朋友

优点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

缺点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

薪资范围

58个数据点

Mid/L4

Mid/L4 · Design Engineer

6份报告

$139,837

年薪总额

基本工资

$124,197

股票

-

奖金

-

$110,434

$186,828

面试经验

1次面试

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving