招聘
必备技能
Circuit simulation
EM/IR analysis
PDK knowledge
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
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Design and develop custom IC design flow to address future and immediate customer requirements
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Responsible for the technical specification of new enhancements to deliver high quality software release
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Provide technical support and trainings for Cadence business
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Communicate with global cross-functional teams to create technical solutions and including involvement with customer engagement
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Documentation of the design flow
Requirement
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BS/MS in Computer Science
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4+ years of experience with custom IC circuit design flow using Virtuoso; layout design experience is a plus
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Expertise in circuit simulation, reliability, EM/IR analysis and post layout simulation
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Solid knowledge of PDK
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planar and finFET experience is a plus
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PDK experience is a plus
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Automation and programming experience is a plus
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Strong analysis/debug capability for technical issues
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Collaborative team player with commitment to team success
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Excellent oral and written communication skills
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
缺点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
薪资范围
58个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
新闻动态
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