招聘
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Lead Firmware Engineer
This is an opportunity to join a dynamic and growing team of experienced engineers developing physical layer IP’s for industry-standard high-speed serial-link protocols. The successful candidate will ideally be a highly motivated self-starter who can work independently to complete assigned tasks and collaborate with other members to achieve project milestones. It is expected that the candidate will contribute during all phases of firmware development for high speed SERDES - from architecture development to implementation, verification, testing and customer deployment.
Responsibilities
- Work closely with PHY digital and mixed signal architects to figure out the details of FW functions and sequences. Contribute during firmware architecture development and implementation of the defined firmware features.
- Help to build system level prototype control software to develop/validate adaptation, equalization, and control algorithms for high speed SERDES.
- Implement assigned FW features and work closely with verificationsimulation and validation team to ensure the functionality and robustness of the implemented features.
- Support Fu Sa compliant firmware development. Work closely with verification and validation team to develop and execute test plans for Fu Sa compliant firmware.
- Support of Validation team during electrical and system characterization during post-silicon testing. Identify any FW and HW related functionality and performance issues and implement any necessary FW improvements to address these issues.
- Support Product Engineering, System Validation and Design team to debug IP issues during customer deployment of the IP and provide hot fixes.
- Create and maintain comprehensive documentation related to firmware design, development, bug fixes and compliance testing.
Desired Skills
- B.Tech with 6yrs or M.Tech with 4 yrs in Electrical/Electronics Engineering
- Solid programming knowledge in C/C++ and Python
- Strong problem-solving and communication skills
- Understanding of wireline communication principles and digital signal processing techniques is a plus
- Knowledge in mixed signal circuit design is a plus
- Experience with silicon validation process and debug is a plus
- Experience with digital verification environment and tools is a plus
- Understanding of Fu Sa compliance is a plus
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance and flexible hours
Supportive and collaborative team environment
Good benefits and stable company
缺点
Below market compensation and pay
Limited growth and advancement opportunities
Heavy workload and long hours during peak times
薪资范围
66个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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