
Leading company in the technology industry
Senior Principal Functional Verification Engineer - Applied ML
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position Overview
We are seeking a results driven Pre-Silicon Verification Engineer with extensive experience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models at scale, as well as accomplished software engineers with proven expertise in product development and deployment. This person will to be part of the ChipStack AI Super Agent team in San Jose, CA - working on the world’s first agentic AI platform that autonomously designs and verifies chips with up to 10× productivity gains. Cadence has been nominated as a Great Place to Work globally and in Brazil, and is also a Fortune 100 Best Companies to Work For.
Key Responsibilities
- Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
- Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
- Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
- Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
- Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.
- Maintain current knowledge of advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth.
Required Qualifications
- BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
- Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM.
- Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.
- Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC).
- Strong programming skills in Verilog, System Verilog and Python
- Excellent communication skills and the ability to thrive in a team-oriented environment.
- Self-motivated, with a proactive approach to problem solving, continuous learning, and innovation.
- Exposure to LLMs and ML technologies like RAG, RFT, RL, and Agentic frameworks would be a plus.
The Cadence Advantage
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
We’re doing work that matters. Help us solve what others can’t.
閲覧数
0
応募クリック
0
Mock Apply
0
スクラップ
0
類似の求人

Test Senior Lead - ITV – HVS – Night Shift
Aptiv · Bangalore, India

Sentinel Manufacturing / Principal Manufacturing Engineer 18189*
Northrop Grumman · Roy, UT

Member of Technical Staff - Systems (Austin, TX)
Aptiv · USA Remote Worksite

Principal Statistical Programmer, R Programming
IQVIA · Durham, North Carolina, United States of America

Senior Software Engineer
HPE · Tel Aviv, Israel
Cadenceにつ いて

Cadence
PublicCadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.
5,001-10,000
従業員数
San Jose
本社所在地
$8.5B
企業価値
レビュー
10件のレビュー
3.9
10件のレビュー
ワークライフバランス
3.8
報酬
2.7
企業文化
4.2
キャリア
3.2
経営陣
2.8
72%
知人への推奨率
良い点
Flexible work arrangements and remote options
Great company culture and collaborative team
Good benefits and job security
改善点
Below average compensation and salary
High workload and overwhelming at times
Limited career advancement opportunities
給与レンジ
75件のデータ
Junior/L3
Junior/L3 · Data Analyst
1件のレポート
$91,103
年収総額
基本給
$85,276
ストック
-
ボーナス
$5,827
$59,612
$139,984
面接レビュー
レビュー1件
難易度
3.0
/ 5
期間
14-28週間
面接プロセス
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
よくある質問
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
最新情報
Cadence Design Systems, Inc. $CDNS Shares Bought by Mitsubishi UFJ Trust & Banking Corp - MarketBeat
MarketBeat
News
·
1w ago
Cadence Design Systems Rides AI Wave in Earnings - TipRanks
TipRanks
News
·
1w ago
Teen killed, older sister being taken off life support after crash - WSB-TV
WSB-TV
News
·
1w ago
Cadence lifts annual revenue forecast on sustained AI chip-design boom - Reuters
Reuters
News
·
1w ago