招聘
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
You will be responsible for building, developing and driving a sales pipeline for our Design IP technology in key accounts across multiple Nor Am regions.
Responsibilities include developing and managing a sales pipeline while driving market penetration, adoption and revenue. You will work closely with and manage multi-functional teams including Application Engineers, Business Unit Marketing, Legal, Finance, Cadence executives and the Cadence EDA software sales team to achieve sales targets in the region.
You will possess a proven track record of selling semiconductor Intellectual Property (IP) technology to organizations spanning small startups to large enterprises. You should have a solid understanding of Memory Interface, Protocol, and Connectivity IP, and how to position 3rd party IP in a highly competitive landscape. You should also have strong strategic selling experience and success delivering large ($1M+) license deals.
Role Requirements:
- Hands on, self-starter who can demonstrate intuitiveness and creativity to drive complex strategic deals
- Ability to generate, develop, qualify, and drive new business opportunities in the region, including:Pipeline development
- Opportunity management
- Manage contract negotiations (business and legal) with customers and Cadence functional teams
- Meet/Exceed quarterly and annual revenue targets
- Ability to articulate value propositions of Design IP products to executive management, marketing, architects, engineering teams within a customer’s organization.
- Manage technical and marketing teams to develop and execute strategies for proliferation of the technology in the region
- Provide market and account feedback to the Design IP Business Unit to drive product roadmaps and strategies.
- Track activities and provide reports to management, BU and executive personnel on account strategies activities and progress
- Develop and execute against strategic sales plans
Key Qualifications:
- Minimum 5 years in licensing of Semiconductor IP technology
- BSEE or equivalent (MBA a plus)
- Strong background in technology
- Experience working with small start-ups to large enterprise accounts driving complex, differentiated technology
- Passion to develop and apply strategic selling skills
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
缺点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
薪资范围
58个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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