
Leading company in the technology industry
Functional Verification Engineer - Applied ML
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.About Us Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Position Overview
Cadence Design Systems Inc. is looking for a motivated and results driven Pre-Silicon Verification Engineer with extensive experience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will be p art of the ChipStack AI Super Agent team and will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models at scale, as well as accomplished software engineers with proven expertise in product development and deployment. You will be working on the world’s first agentic AI platform that autonomously designs and verifies chips with up to 10× productivity gains.
Key Responsibilities
- Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
- Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
- Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
- Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
- Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.
- Maintain current knowledge of advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth.
Required Qualifications
- BS with a minimum of 4 years of experience OR MS with a minimum of 2 years of experience OR new PhD Graduate
- Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM.
- Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.
- Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC).
- Strong programming skills in Verilog, System Verilog and Python
- Excellent communication skills and the ability to thrive in a team-oriented environment.
- Self-motivated, with a proactive approach to problem solving, continuous learning, and innovation.
- Exposure to LLMs and ML technologies like RAG, RFT, RL, and Agentic frameworks would be a plus.
The Cadence Advantage
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
10条评价
3.9
10条评价
工作生活平衡
3.8
薪酬
2.7
企业文化
4.2
职业发展
3.2
管理层
2.8
72%
推荐率
优点
Flexible work arrangements and remote options
Great company culture and collaborative team
Good benefits and job security
缺点
Below average compensation and salary
High workload and overwhelming at times
Limited career advancement opportunities
薪资范围
75个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试评价
1条评价
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
最新动态
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