refresh

トレンド企業

トレンド企業

採用

求人Cadence

Lead Application Engineer

Cadence

Lead Application Engineer

Cadence

BANGALORE

·

On-site

·

Full-time

·

2mo ago

必須スキル

Analog layout design

Virtuoso

IC design

Physical verification

Skill scripting

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Your role will be to meet customers/prospects and identify & qualify the opportunities, work out agreeable, equally importantly achievable, evaluation criteria, run through the evaluation and convert the opportunities into business and help customers to deploy the tool and get it running into production at the earliest. It requires a very good understanding of customer flow and a good analytical ability to resolve issues impacting production schedule.
  • Hands–on knowledge of Advance Node layout and design rules would be a plus.
  • The role demands a close interaction with R&D and Product Engineering team for implementation of new features and bug fixes.
  • As the job requires an extensive interaction with customers for issue resolution and identifying opportunities to proliferate Cadence technologies, at the same time a closer interaction with R&D and other stakeholders, it demands an excellent customer and communication skills, and the leadership qualities.
  • This position requires solid understanding of IC design technology and foundry process/methodology in analog layouts.
  • It is essential to have a very good understanding of analog layout design fundamentals, advance node virtuoso techfile constraints and in-depth knowledge and hands-on experience on writing skill scripts to perform various layout automation tasks.
  • The candidate should have knowledge of complete analog back-end flow from top level floorplanning down to complex block level layouts, physical verification, extraction, EMIR analysis etc, with proficiency in Cadence layout tools specifically Virtuoso with advance node exposure.
  • Prior Design experience using Cadence CustomIC Physical Design tools (Virtuoso) and flows including chip integration and signoff is an added advantage.
    • B.Tech or equivalent with 3 to 7 years of relevant experience.

We’re doing work that matters. Help us solve what others can’t.

総閲覧数

0

応募クリック数

0

模擬応募者数

0

スクラップ

0

Cadenceについて

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

従業員数

San Jose

本社所在地

$8.5B

企業価値

レビュー

4.0

10件のレビュー

ワークライフバランス

4.2

報酬

2.8

企業文化

4.1

キャリア

3.2

経営陣

3.4

72%

友人に勧める

良い点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

改善点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

給与レンジ

58件のデータ

Junior/L3

Junior/L3 · Data Analyst

1件のレポート

$91,103

年収総額

基本給

$85,276

ストック

-

ボーナス

$5,827

$59,612

$139,984

面接体験

1件の面接

難易度

3.0

/ 5

期間

14-28週間

面接プロセス

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

よくある質問

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving