
Leading company in the technology industry
Design Engineering Architect
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Design Engineering Architect – Roles & Responsibilities
- Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations
- Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements
- Good understanding of PHY/IOcircuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offs
- Act as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offs
- Collaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals
- Provide expert‑level IP support to customers, including architecture clarification, feature customization
- Work cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented
- Review and guide architecture specifications, design reviews, and technical documentation
- Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer‑driven requirements
- Demonstrate strong communication, accountability, and technical ownership across internal and external interactions
Required Qualifications
- M.S. degree in Electrical Engineering, Computer Engineering, or related field
- Minimum 15 years of industry experience in memory interface PHY, high‑speed IO, or related domains
- Strong background in memory interface PHYs,JEDEC standards, and protocols
- Proven ability to own customer‑facing technical engagements and drive issues to closure
- Excellent written and verbal communication skills
The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
10条评价
3.9
10条评价
工作生活平衡
3.8
薪酬
2.7
企业文化
4.2
职业发展
3.2
管理层
2.8
72%
推荐率
优点
Flexible work arrangements and remote options
Great company culture and collaborative team
Good benefits and job security
缺点
Below average compensation and salary
High workload and overwhelming at times
Limited career advancement opportunities
薪资范围
75个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试评价
1条评价
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
最新动态
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Teen killed, older sister being taken off life support after crash - WSB-TV
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·
1w ago
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·
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