トレンド企業

Cadence
Cadence

Leading company in the technology industry

Design Engineering Architect

職種エンジニアリング
経験ミドル級
勤務地SAN JOSE
勤務オンサイト
雇用正社員
掲載1週間前
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Design Engineering Architect – Roles & Responsibilities

  • Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations
  • Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements
  • Good understanding of PHY/IOcircuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offs
  • Act as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offs
  • Collaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals
  • Provide expert‑level IP support to customers, including architecture clarification, feature customization
  • Work cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented
  • Review and guide architecture specifications, design reviews, and technical documentation
  • Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer‑driven requirements
  • Demonstrate strong communication, accountability, and technical ownership across internal and external interactions

Required Qualifications

  • M.S. degree in Electrical Engineering, Computer Engineering, or related field
  • Minimum 15 years of industry experience in memory interface PHY, high‑speed IO, or related domains
  • Strong background in memory interface PHYs,JEDEC standards, and protocols
  • Proven ability to own customer‑facing technical engagements and drive issues to closure
  • Excellent written and verbal communication skills

The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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Cadenceについて

Cadence

Cadence

Public

Cadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.

5,001-10,000

従業員数

San Jose

本社所在地

$8.5B

企業価値

レビュー

10件のレビュー

3.9

10件のレビュー

ワークライフバランス

3.8

報酬

2.7

企業文化

4.2

キャリア

3.2

経営陣

2.8

72%

知人への推奨率

良い点

Flexible work arrangements and remote options

Great company culture and collaborative team

Good benefits and job security

改善点

Below average compensation and salary

High workload and overwhelming at times

Limited career advancement opportunities

給与レンジ

75件のデータ

Junior/L3

Junior/L3 · Data Analyst

1件のレポート

$91,103

年収総額

基本給

$85,276

ストック

-

ボーナス

$5,827

$59,612

$139,984

面接レビュー

レビュー1件

難易度

3.0

/ 5

期間

14-28週間

面接プロセス

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

よくある質問

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving