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Cadence
Cadence

Leading company in the technology industry

Design Engineering Architect

RoleEngineering
LevelMid Level
LocationSAN JOSE
WorkOn-site
TypeFull-time
Posted1 week ago
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Design Engineering Architect – Roles & Responsibilities

  • Contribute to PHY architecture development with deep understanding of memory interface PHY IPs (e.g., DDR, LPDDR), including electrical, timing, power, and protocol considerations
  • Drive architecture decisions aligned with JEDEC standards, protocols, and compliance requirements
  • Good understanding of PHY/IOcircuit architecture including TX/RX, clocking, termination, power delivery, and signal integrity trade‑offs
  • Act as a customer‑facing technical architect during pre‑sales, evaluations, and post‑delivery support, clearly articulating architecture choices and trade‑offs
  • Collaborate closely with Sales, Marketing, and Program teams to support customer engagements, RFIs, and technical proposals
  • Provide expert‑level IP support to customers, including architecture clarification, feature customization
  • Work cross‑functionally with design, verification, layout, and silicon validation teams to ensure architectural intent is correctly implemented
  • Review and guide architecture specifications, design reviews, and technical documentation
  • Influence product and technology roadmap planning by identifying future standards, protocol evolution, and customer‑driven requirements
  • Demonstrate strong communication, accountability, and technical ownership across internal and external interactions

Required Qualifications

  • M.S. degree in Electrical Engineering, Computer Engineering, or related field
  • Minimum 15 years of industry experience in memory interface PHY, high‑speed IO, or related domains
  • Strong background in memory interface PHYs,JEDEC standards, and protocols
  • Proven ability to own customer‑facing technical engagements and drive issues to closure
  • Excellent written and verbal communication skills

The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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About Cadence

Cadence

Cadence

Public

Cadence Design Systems, Inc. is an American multinational technology and computational software company headquartered in San Jose, California.

5,001-10,000

Employees

San Jose

Headquarters

$8.5B

Valuation

Reviews

10 reviews

3.9

10 reviews

Work-life balance

3.8

Compensation

2.7

Culture

4.2

Career

3.2

Management

2.8

72%

Recommend to a friend

Pros

Flexible work arrangements and remote options

Great company culture and collaborative team

Good benefits and job security

Cons

Below average compensation and salary

High workload and overwhelming at times

Limited career advancement opportunities

Salary Ranges

75 data points

Junior/L3

Junior/L3 · Data Analyst

1 reports

$91,103

total per year

Base

$85,276

Stock

-

Bonus

$5,827

$59,612

$139,984

Interview experience

1 interviews

Difficulty

3.0

/ 5

Duration

14-28 weeks

Interview process

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

Common questions

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving