招聘
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The candidate will work closely with sales account managers and technical field application engineers supporting technical campaigns by delivering workshops, product demonstrations, training, and onsite support. The candidate will have expert knowledge of the Cadence toolset and/or equivalent competitor toolsets in the context of multiple flows including high-speed signal design, power design, signal integrity and electrical constraints definition. Design experience and industry knowledge of Signal, Power, and Thermal analysis are required, as associated with IC, package, and PCB designs.
The candidate needs to have the ability to analyze the customer's environment and evaluate appropriate solutions. Be knowledgeable and aware of competitive technologies. Anticipates technical issues and develops creative solutions before they become a problem. Takes technical lead on a wide range of projects. Ability to understand high-speed, high-performance signal and power integrity-related issues, and work with peers and other business groups. Able to work on-site with customers without supervision. Able to communicate effectively with Cadence R&D, Product Engineering, Marketing and with customers. Understands customer success criteria and is committed to ensuring customer success.
Requirements;
10+ years’ experience, Bachelors, Master’s or Ph.D. degree in Electrical or Electronics Engineering. In-depth knowledge of EDA industry with strong background in Signal Integrity, Power Integrity, Electromagnetics, Thermal, and RF applications related to IC Package and PCB Design are required. Candidate should have experience in Cadence Allegro platform tools such as Sigrity, Clarity, PCB Editor, APD or competitive tools in these areas. The candidate must possess excellent written and verbal communication skills. Be able to present and clearly articulate solutions individually, and in front of medium to large groups.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
缺点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
薪资范围
58个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
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