招聘
必备技能
Python
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Overview
The Sr Application Engineer Architect will serve as a senior technical leader within Cadence’s North America Field Applications Team, driving strategic customer engagements and influencing next-generation EDA & Agentic-AI solutions. This role demands exceptional technical depth, proven leadership, and the ability to align cross-functional teams toward delivering advanced design solutions for leading semiconductor companies.
Key Responsibilities
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Strategic Leadership: Define and execute technical engagement strategies for top semiconductor design team, ensuring alignment with corporate objectives and customer success metrics.
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Customer Advocacy: Act as a trusted advisor for executive-level stakeholders, guiding adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes (3nm and below).
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Team Development: Lead and mentor a high-performing team of Application Engineers, fostering technical excellence and career growth.
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Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
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Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for Synthesis, P&R, STA, IR Drop, and power/timing closure.
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Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.
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Operational Excellence: Establish best practices for engagement models, resource planning, and technical escalations to ensure timely and successful project execution.
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Qualifications
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20+ years of experience in IC design implementation and signoff, with demonstrated success in managing large-scale technical programs.
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BS/MS in Electrical Engineering, Computer Engineering, or related field.
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Deep expertise in digital design fundamentals, advanced node implementation (3nm and below), and EDA tool ecosystems.
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Proven track record of leading technical teams and driving customer success at executive levels.
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Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
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Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
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Prior experience with Cadence tools (Genus, Innovus, Tempus, Voltus, Conformal, Cerebrus) and competitive solutions highly desirable.
The annual salary range for California is $187,600 to $348,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
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关于Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
员工数
San Jose
总部位置
$8.5B
企业估值
评价
4.0
10条评价
工作生活平衡
4.2
薪酬
2.8
企业文化
4.1
职业发展
3.2
管理层
3.4
72%
推荐给朋友
优点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
缺点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
薪资范围
58 个数据点
Junior/L3
Junior/L3 · Data Analyst
1份报告
$91,103
年薪总额
基本工资
$85,276
股票
-
奖金
$5,827
$59,612
$139,984
面试经验
1次面试
难度
3.0
/ 5
时长
14-28周
面试流程
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
常见问题
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
新闻动态
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