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求人Cadence

Principal Design Engineer

Cadence

Principal Design Engineer

Cadence

PUNE

·

On-site

·

Full-time

·

1mo ago

必須スキル

Python

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Performance Modeling Engineer

Location – India (Pune)

Summary

We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.

Responsibilities

  • Develop cycle-level performance models in SystemC or C++
  • Correlate performance models to match RTL configurations and traffic conditions
  • Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
  • Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
  • Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
  • Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Required Skills

  • BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
  • 8+ years of experience in hardware modeling, functional or performance
  • Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
  • Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs

Additional Skills

  • Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
  • Understand memory protocols and timing – DDR4, DDR5, LP4, LP5
  • Experience using performance simulators – Memory Controller, NoC, CPU models
  • Coding in Python and familiarity with packages like Pandas, Matplotlib
  • Experience working with performance benchmarks – SPEC, STREAM, etc
  • Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies

We’re doing work that matters. Help us solve what others can’t.

総閲覧数

2

応募クリック数

0

模擬応募者数

0

スクラップ

0

Cadenceについて

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

従業員数

San Jose

本社所在地

$8.5B

企業価値

レビュー

4.0

10件のレビュー

ワークライフバランス

4.2

報酬

2.8

企業文化

4.1

キャリア

3.2

経営陣

3.4

72%

友人に勧める

良い点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

改善点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

給与レンジ

58件のデータ

Junior/L3

Junior/L3 · Data Analyst

1件のレポート

$91,103

年収総額

基本給

$85,276

ストック

-

ボーナス

$5,827

$59,612

$139,984

面接体験

1件の面接

難易度

3.0

/ 5

期間

14-28週間

面接プロセス

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

よくある質問

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving