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职位Cadence

Principal Design Engineer

Cadence

Principal Design Engineer

Cadence

PUNE

·

On-site

·

Full-time

·

1mo ago

必备技能

Python

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Performance Modeling Engineer

Location – India (Pune)

Summary

We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.

Responsibilities

  • Develop cycle-level performance models in SystemC or C++
  • Correlate performance models to match RTL configurations and traffic conditions
  • Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
  • Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
  • Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)
  • Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Required Skills

  • BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar
  • 8+ years of experience in hardware modeling, functional or performance
  • Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
  • Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs

Additional Skills

  • Understand RTL-Verilog, SV, UVM and experience analyzing waveforms
  • Understand memory protocols and timing – DDR4, DDR5, LP4, LP5
  • Experience using performance simulators – Memory Controller, NoC, CPU models
  • Coding in Python and familiarity with packages like Pandas, Matplotlib
  • Experience working with performance benchmarks – SPEC, STREAM, etc
  • Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies

We’re doing work that matters. Help us solve what others can’t.

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关于Cadence

Cadence

Cadence

Public

Cadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.

5,001-10,000

员工数

San Jose

总部位置

$8.5B

企业估值

评价

4.0

10条评价

工作生活平衡

4.2

薪酬

2.8

企业文化

4.1

职业发展

3.2

管理层

3.4

72%

推荐给朋友

优点

Good work-life balance

Supportive and collaborative team environment

Flexible work arrangements

缺点

Below market compensation

Limited career advancement opportunities

Heavy workload and long hours

薪资范围

58个数据点

Junior/L3

Junior/L3 · Data Analyst

1份报告

$91,103

年薪总额

基本工资

$85,276

股票

-

奖金

$5,827

$59,612

$139,984

面试经验

1次面试

难度

3.0

/ 5

时长

14-28周

面试流程

1

Application Review

2

Recruiter Screen

3

Technical Phone Screen

4

Onsite/Virtual Interviews

5

Final Decision

常见问题

Technical Knowledge

Behavioral/STAR

Past Experience

Problem Solving