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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Title: Lead Software Engineer
Location: Cambridge, United Kingdom
Reports to: Software Engineering Director
Job Overview:
Genus Synthesis Solution is a leading technology tool for synthesizing digital designs from RTL (Register Transfer Language) specifications (Verilog or VHDL) into netlists based on standard cells. Trusted by over 400 customers worldwide, Genus enables chip design through cutting-edge optimization for timing, area, and power.
Genus is complemented by Chip Ware®, an IP library of configurable, off-the-shelf components that deliver best-in-class hardware quality across power, area, and delay requirements.
As part of our expansion, we are seeking talented individuals who share our passion for computer arithmetic and our commitment to quality, innovation, and insight. This role offers a unique opportunity to work across software and hardware development, applied research, and direct customer engagement, making you a true subject matter expert in the field.
Job Responsibilities:
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Collaborate within a team to design, optimize, verify, and document a library of high-quality arithmetic components (e.g., floating-point operators) for chip designers.
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Ensure components are robust, efficient, and easy to integrate.
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Drive innovation in system design and optimisation for timing, area, and power.
Job Qualifications:
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Strong academic background (Master’s / PhD in Mathematics, Physics, Computer Science, or Electrical Engineering).
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Eagerness to learn how to build, optimize, and verify complex arithmetic operators for microchips.
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Programming experience is a plus (especially C, C++, Python, or System Verilog).
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Excellent creative and analytical problem-solving skills.
Why Join Us?
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Impactful Work: Your contributions will directly influence the design of next-generation chips used by leading technology companies worldwide.
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Cutting-Edge Technology: Work with advanced synthesis tools and IP libraries that set industry standards.
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Growth & Learning: Gain deep expertise in computer arithmetic, hardware optimization, and software development in a collaborative environment.
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Innovation Culture: Be part of a team that values creativity, problem-solving, and continuous improvement.
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Global Reach: Engage with customers and projects across the globe, shaping solutions that power modern electronics.
Check what we can offer you:
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Competitive salary
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25 days holiday per year
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Private Medical and Dental plans, Income Protection and Life Insurance
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Group Personal Pension Plan
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Cycle to work scheme and gym subsidy
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5 days paid time to volunteer to give back to our communities
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Employee Stock Purchase Plan
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The opportunity to work for a Great Place to Work© & Fortune 100 organization
Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
We’re doing work that matters. Help us solve what others can’t.
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Cadenceについて

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
従業員数
San Jose
本社所在地
$8.5B
企業価値
レビュー
4.0
10件のレビュー
ワークライフバランス
4.2
報酬
2.8
企業文化
4.1
キャリア
3.2
経営陣
3.4
72%
友人に勧める
良い点
Good work-life balance
Supportive and collaborative team environment
Flexible work arrangements
改善点
Below market compensation
Limited career advancement opportunities
Heavy workload and long hours
給与レンジ
58件のデータ
Junior/L3
Junior/L3 · Data Analyst
1件のレポート
$91,103
年収総額
基本給
$85,276
ストック
-
ボーナス
$5,827
$59,612
$139,984
面接体験
1件の面接
難易度
3.0
/ 5
期間
14-28週間
面接プロセス
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
よくある質問
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
ニュース&話題
Ninety One UK Ltd Cuts Position in Cadence Design Systems, Inc. $CDNS - MarketBeat
MarketBeat
News
·
2d ago
Moran Wealth Management LLC Sells 19,592 Shares of Cadence Design Systems, Inc. $CDNS - MarketBeat
MarketBeat
News
·
2d ago
Cadence Maps Its Future Beyond EDA With Agentic AI and Simulation - HPCwire
HPCwire
News
·
3d ago
Lesser-Known Cadence Design Systems Just Landed Google and Nvidia Deals. Should You Buy CDNS Stock? - Barchart.com
Barchart.com
News
·
3d ago