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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
システム・機能検証 担当アプリケーション・エンジニア
- 応募資格大卒 (電気・電子、コンピュータサイエンス)、またはそれに準じる経験、知識をお持ちの方で新しいことに意欲的にチャレンジ出来る 方
- 経験/スキル6年以上のHDL設計・検証の業務経験を持つ方
- EDAツール(主に機能シュミレータ、デバッガ)の利用経験がある方
- EDA ツール自体の評価などの経験がある方
- ハードウェアエミュレータやFPGAを使用した製品開発の経験がある方であればお尚よし
- 業務を効率良く行うためのプログラミング・スキルを持つ方(シェル、C/C++, Perl、Tcl、Python、Ruby等の活用経験)
- 検証言語(HDL/System Verilog/e/SystemC)や検証メソドロジ(UVM等)による検証環境構築もしくは機能検証の経験がある方
- 顧客が抱える検証課題に対して最適なソリューションを提供する事ができ、
顧客と良好な信頼関係を継続して構築できる方 - 日本語・英語でのメールのやり取り及び技術的会話に支障がない事
- 問題解決能力があり、モチベーションを高く持って自ら業務を進められる方
- 自らの活動範囲に制限を設けず、何事にも貪 欲に取り組み、新しい技術を吸収しながら成長していける方
- 業務内容ケイデンスの機能検証製品に関する顧客向け技術プリセールス、及び、ポストサポート業務
Application Engineer – Functional Verification
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Qualification Requirements
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Bachelor’s degree in Computer Science, Electrical/Electronic Engineering, or related field
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Has the knowledge and desire to take on new challenges
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Experiences/Skills
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At least 6 years’ experience in HDL design and verification
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Experience in using EDA tools (mainly functional simulators and debuggers)
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Experience in evaluating EDA tools
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Experience of Mixed-Signal verification is better
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Experience in product development using Hardware Emulator or FPGA is better
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Programming skills to efficiently perform tasks (practical experience in shell scripting, C/C++, Perl, Tcl, Python, Ruby, etc.)
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Experience in construction of verification environments or functional verification using verification languages(HDL/System Verilog/e/SystemC) or verification methodologies (UVM, etc.)
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Can provide optimal solutions to the verification tasks that customers have and can continue to build good trust with customers
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Can communicate in both Japanese and English (email exchange and technical discussion)
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Ability to solve problems; can work independently with high motivation
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Does not put restrictions on scope of work, engages in everything with a passion, and can grow while absorbing new technologies
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Job Description
Technical pre-sales and post-sales services for customers of Cadence's functional verification products
We’re doing work that matters. Help us solve what others can’t.
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About Cadence

Cadence
PublicCadence Design Systems provides electronic design automation (EDA) software, hardware, and IP for designing and verifying electronic systems and semiconductors.
5,001-10,000
Employees
San Jose
Headquarters
Reviews
3.3
7 reviews
Work Life Balance
2.0
Compensation
2.5
Culture
1.8
Career
2.0
Management
1.5
15%
Recommend to a Friend
Pros
Built strong client relationships
Useful for repetitive tasks
Employment opportunities
Cons
Poor management and micromanagement
Lack of career growth opportunities
Technical architecture and code quality issues
Salary Ranges
65 data points
Junior/L3
Junior/L3 · Data Analyst
1 reports
$91,103
total / year
Base
$85,276
Stock
-
Bonus
$5,827
$59,612
$139,984
Interview Experience
1 interviews
Difficulty
3.0
/ 5
Duration
14-28 weeks
Interview Process
1
Application Review
2
Recruiter Screen
3
Technical Phone Screen
4
Onsite/Virtual Interviews
5
Final Decision
Common Questions
Technical Knowledge
Behavioral/STAR
Past Experience
Problem Solving
News & Buzz
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